John M. Emmert

Dynamic fault tolerance in FPGAs via partial reconfiguration

In this paper we present an on-line, multi-level fault tolerant (FT) technique for system functions and applications mapped to partially and dynamically reconfigurable FPGAs. Our method is based on the roving self testing areas (STARs) fault detection/location strategy presented in Abramovici et al. (1999). In STARs, the area under test uses partial reconfiguration properties to modify the configuration of the area under test without affecting the configuration of the system function and dynamic reconfiguration properties to allow uninterrupted execution of the system function while reconfiguration takes place. In this paper we take this one step further. Once a fault (or multiple faults) is detected we dynamically reconfigure the working area application around the fault with no additional system function interruption (other than the interruption when a STAR moves to a new location). We also apply the concept of partially usable blocks to increase fault tolerance. Our method has been successfully implemented and demonstrated on the ORCA 2CA series FPGAs from Lucent Technologies.

Online BIST and BIST-based diagnosis of FPGA logic blocks

We present the first online built-in self-test (BIST) and BIST-based diagnosis of programmable logic resources in field-programmable gate arrays (FPGAs). These techniques were implemented and used in a roving self-testing areas (STARs) approach to testing and reconfiguration of FPGAs for fault-tolerant applications. The BIST approach provides complete testing of the programmable logic blocks (PLBs) in the FPGA during normal system operation. The BIST-based diagnosis can identify any group of faulty PLBs, then applies additional diagnostic configurations to identify the faulty look-up table or flip-flop within a faulty PLB. The ability to locate defective modules inside a PLB enables a new form of fault-tolerance that reuses partially defective PLBs in their fault-free modes of operation.

Incremental routing in FPGAs

In this paper we present algorithms for incrementally routing circuits mapped to field-programmable gate arrays (FPGAs). The algorithms work well for ripping up and rerouting nets connected to small numbers of displaced logic blocks. Additionally the algorithms are sequential and compact, therefore making them ideal for embedding in hardware. Given an FPGA with a readable as well as writable configuration memory, these algorithms require no prior knowledge of the mapped circuits netlist. Experimental results indicate our router works well for fault tolerance and other applications.

Partial reconfiguration of FPGA mapped designs with applications to fault tolerance and yield enhancement

Field-programmable gate arrays have the potential to provide reconfigurability in the presence of faults. In this paper, we have investigated the problem of partially reconfiguring FPGA mapped designs. We present a maximum matching based algorithm to reconfigure the placement on an FPGA with little or no impact on circuit performance. Experimental results indicate the algorithm works well for both fault tolerance and reconfigurable computing applications. We also present the motivation and feasibility of using a similar approach for dynamic circuit reconfigurability.

Improving on-line BIST-based diagnosis for roving STARs

We present improvements to our on-line BIST-based diagnosis technique originally used in the roving STARs approach. The enhanced technique starts with a new method of analyzing the BIST results, and employs the original divide-and-conquer method as a second phase only when the first phase fails or it does not achieve maximum diagnostic resolution. The combined technique significantly reduces the diagnosis time, improves the resolution in several cases, and also requires less fault-free resources.

On-line BIST and diagnosis of FPGA interconnect using roving STARs

Presents the first on-line BIST and BIST-based diagnostic approach for the programmable interconnect resources in FPGAs. This interconnect BIST is used in the roving STARs approach. The technique provides a complete BIST of the programmable interconnect followed by high-resolution diagnostics to support reconfiguration around the fault for fault-tolerant applications. We have successfully implemented this BIST approach on the ORCA 2C series FPGA and present the results of testing and diagnosing known defective FPGAs.

Bridging fault extraction from physical design data for manufacturing test development

In this paper we explore the process of extracting potential bridging fault sites from the physical design database for VLSI devices by using standard extraction tools for fringe and overlap capacitance. We then use the extracted capacitance to create a list of potential bridging fault sites ordered to reflect the relative probability of a bridging fault occurring at each site. As a result, potential bridging fault sites can be rank-ordered for manufacturing test development such that the most likely site can be targeted first. In this way we improve the overall efficiency and effectiveness of the test development process. We have implemented this technique for the Delta 39K/sup TM/ series of complex programmable logic devices by Cypress Semiconductor and describe the results obtained.

A methodology for fast FPGA floorplanning

Floorplanning is an important problem in FPGA circuit mapping. As FPGA capacity grows, new innovative approaches will be required for efficiently mapping circuits to FPGAs. In this paper we present a macro based floorplanning methodology suitable for mapping large circuits to large, high density FPGAs. Our method uses clustering techniques to combine macros into clusters, and then uses a tabu search based approach to place clusters while enhancing both circuit routability and performance. Our method is capable of handling both hard (fixed size and shape) macros and soft (fixed size and variable shape) macros. We demonstrate our methodology on several macro based circuit designs and compare the execution speed and quality of results with commercially available CAE tools. Our approach shows a dramatic speedup in execution time without any negative impact on quality.

A Fault Tolerant Technique for FPGAs

In this paper we present a fault tolerant (FT) technique for field programmable gate arrays (FPGAs) that is based on incrementally reconfiguring circuits and applications that have been previously placed and routed. Our technique targets both logic faults and interconnect faults, and our algorithms can be applied to either static or run-time reconfigurable FPGAs. The algorithm for reconfiguring designs in the presence of logic faults uses a matching technique. The matching technique requires no preplaced, spare logic resources and is capable of handling groups of faults. Experimental results indicate there is little or no impact on circuit performance for low numbers of reconfigured logic blocks. For interconnect faults, we present a rip-up and reroute strategy. Our strategy is based on reading back the FPGA configuration memory, so no netlist is required for rerouting around faulty resources. Experimental results indicate high incremental routability for low numbers of interconnect faults. We also lay the foundation for applying our approach to yield enhancement.

A new bridging fault model for more accurate fault behavior

We describe a new bridging fault model which more accurately simulates the behavior of bridging faults that have been observed as a result of manufacturing fabrication defects in tightly packed logic structures.