John M. Pierce

Characterization of mechanical planarization processes

A square-wave test structure is described which provides a useful vehicle for characterizing planarization processes. The structure is designed for easy replication in different laboratories to allow comparison of planarization methods in spite of their inherent pattern sensitivity. Results obtained for a number of mechanical planarization processes on this structure are presented. A planarization rate parameter p is defined and used to describe the planarization of features in the width range of 1-10 mm, a range which is important because of the effects of long-range pattern density variations in VLSI chips. Polishing pad structure and condition are found to be the most important determiners of p, and results for several commercially available pads are reported. Mechanical planarization adequate to handle the interlayer dielectric (ILD) planarization requirements of most chips is demonstrated.<<ETX>>

The mechanical planarization of interlevel dielectrics for multilevel interconnect applications

A description is given of the application of mechanical planarization to the interlevel dielectric (ILD) of a multilevel interconnect system. Experimental results obtained from large 80K, two-level metal CMOS gate arrays (0.7 cm/sup 2/) having mechanically planarized ILD indicated leveling lengths on the order of 0.5 cm and excellent via functionality. Surface leveling with variations of less than 200 AA was readily achieved over the whole gate array die. No detrimental effects were observed in a fully functional die when compared with devices using sacrificial spin-on glass. The results of this study indicate that mechanical planarization will make a critical contribution to the fabrication of ULSI devices having 0.25- mu m interconnect feature sizes.<<ETX>>