Ali A. Iranmanesh

A 0.8- mu m advanced single-poly BiCMOS technology for high-density and high-performance applications

A single-poly, 0.8- mu m advanced BiCMOS technology, ABiC IV, is described. It has both high-performance CMOS and 15-GHz bipolar transistors. The process described has been developed for high-performance application-specific IC (ASIC) applications with emphasis on embedded CMOS, BiCMOS, or emitter-coupled logic (ECL) memory as well as BiCMOS and ECL gate arrays and standard cells. The key features of this BiCMOS process are twin buried layers, low encroachment recessed oxide isolation, a double-diffused bipolar process, a single-poly architecture with silicided local interconnection, and four levels of metallization with tungsten plugs. Ring-oscillator gate delays of about 125 ps for BiCMOS, less than 90 ps for CMOS, and about 48 ps for ECL were obtained with this process. >

0.6 amu;m, single poly advanced BiCMOS (ABiC IV) technology for ASIC applications

An advanced BiCMOS technology (ABiC IV), developed by integration of high-performance CMOS devices with a state of the art bipolar process, is presented. The core bipolar process is the fourth generation of the advanced single poly emitter coupled technology (ASPECT). Gate delays of 47 psec, 110 psec and 120 psec have been achieved for unloaded ECL, CMOS and BiCMOS gates, respectively. In addition to silicided poly for local interconnection, this technology offers four layers of metallization with chemical vapor deposition (CVD) tungsten-filled contacts and vias. Interconnection delays are 1 ps/mil. ABiC technology is most attractive for high-performance 50K to 100K gate ECL logic arrays, 100K to 200K gate CMOS/BiCMOS logic arrays, and high-density ASIC products requiring embedded memories

The effect of isolation edge profile on the leakage and breakdown characteristics of advanced bipolar transistors

The authors describe the effect of the isolation edge profile on the leakage and breakdown characteristics of advanced poly emitter NPN bipolar transistors. It is shown that the isolation edge profile can cause considerable base narrowing and reduction of the Gummel number, thus controlling the collector-emitter breakdown voltage, BV/sub ceo/, and the collector-emitter leakage current, I/sub ceo/. The reduction in BV/sub ceo/ can become severe enough so that the devices cannot operate at the maximum supply voltages used in emitter coupled logic (ECL) and BiCMOS circuits. The vertical scaling of the intrinsic device will be constrained under these circumstances to meet the required circuit breakdown characteristics, compromising device parameters such as beta and the unity gain cutoff frequency. Therefore device isolation can control key device parameters, thus becoming a major limiting factor in the development of high-performance bipolar devices.<<ETX>>

A 0.8 mu m advanced single poly BiCMOS technology for high density and high performance applications

A single poly, 0.8 mu m BiCMOS technology having both high-performance CMOS and 14 GHz ASPECT III n-p-n transistors is described. The advanced features of this BiCMOS technology include a low encroachment, defect-free recessed oxide isolation process, self-aligned integrated well taps for MOS devices, double diffused bipolar process, silicided local interconnect, and four levels of metallization with tungsten plugs. Ring oscillator gate delays of <150 ps BiCMOS, <90 ps CMOS, and<50 ps ECL are obtained with this process. This technology is most applicable to high-performance/high-density standard cell ECL gate array circuits requiring embedded memory.<<ETX>>

Submicron BiCMOS technologies for supercomputer and high speed system implementation

Submicron process technologies that allow a full implementation of CPU, first-level cache, second-level cache, and the main memory in the BiCMOS approach are described. CPU standard cells up to 100 K ECL gate density with embedded CMOS and BiCMOS SRAM, X9 cache memories, and 1-Meg ECL I/O SRAMs with less than 7-ns access time have been achieved.<<ETX>>

Application of lightly doped buried-layer for the reduction of the interconnection and junction capacitances

Interconnection delay plays a dominant role in determining the speed performance of todays integrated circuits. It is shown that the formation of a lightly doped buried layer (LDBL) reduces the capacitance of wiring leads and bonding pads with respect to the substrate. LDBL also improves the collector-to-substrate capacitance of npn transistors as well as the tub-to-substrate capacitance of MOS transistors. As a result the speed performance of the products employing this technique is significantly improved. Because of the relative simplicity of the process, the ratio of percent delay reduction to percent cost increase is expected to be smaller than for any alternative approach.<<ETX>>