John Maltabes

32 nm imprint masks using variable shape beam pattern generators

Imprint lithography has been included on the ITRS Lithography Roadmap at the 32, 22 and 16 nm nodes. Step and Flash Imprint Lithography (S-FIL ®) is a unique method that has been designed from the beginning to enable precise overlay for creating multilevel devices. A photocurable low viscosity monomer is dispensed dropwise to meet the pattern density requirements of the device, thus enabling imprint patterning with a uniform residual layer across a field and across entire wafers. Further, S-FIL provides sub-100 nm feature resolution without the significant expense of multi-element, high quality projection optics or advanced illumination sources. However, since the technology is 1X, it is critical to address the infrastructure associated with the fabrication of templates. For sub-32 nm device manufacturing, one of the major technical challenges remains the fabrication of full-field 1x templates with commercially viable write times. Recent progress in the writing of sub-40 nm patterns using commercial variable shape e-beam tools and non-chemically amplified resists has demonstrated a very promising route to realizing these objectives, and in doing so, has considerably strengthened imprint lithography as a competitive manufacturing technology for the sub 32nm node. Here we report the first imprinting results from sub-40 nm full-field patterns, using Samsungs current flash memory production device design. The fabrication of the template is discussed and the resulting critical dimension control and uniformity are discussed, along with image placement results. The imprinting results are described in terms of CD uniformity, etch results, and overlay.

Current state of 300-mm lithography in a pilot line environment

SEMICONDUCTOR300 (SC300) is the first pilot manufacturing facility for 300 mm wafers in the world. This company, a joint venture between Infineon Technologies and Motorola, is working on developing a 300 mm manufacturing tool set. The pilot line contains a full compliment of tools for 0.24 micrometer ground rule 64 M DRAM manufacturing. The 64 M DRAM was chosen for the ability to easily benchmark against 200 mm 64 M DRAM manufacturing data from the sister factory. Currently, testing on structures with less than 0.20 micrometer ground rules is occurring the pilot line. In this paper we present the performance of the initial lithography tool set installed at SC300. Several lots of wafers with measurable yield have been produced. These lots have produced data on overlay, critical dimensions, and run-to-run, wafer-to-wafer and within-wafer performance of the various lithography layers. We now have preliminary data on the comparison of 200 mm tools to 300 mm tools in terms of footprint, throughput, reliability, and productivity gains for equivalent square centimeters of silicon. With this data we can start to predict what performance we should expect from 300 mm manufacturing lithography tools.

Mighty high-T lithography for 65-nm generation contacts

Contact patterning for the 65nm device generation will be an exceedingly difficult task. The 2001 SIA roadmap lists the targeted contact size as 90nm with +/-10% CD control requirements of +/-9nm. Defectivity levels must also be below one failure per billion contacts for acceptable device yield. Difficulties in contact patterning are driven by the low depth of focus of isolated contacts and/or the high mask error (MEF) for dense contact arrays (in combination with expected reticle CD errors). Traditional contact lithography methods are not able to mitigate both these difficulties simultaneously. Inlaid metal trench patterning for the 65nm generation has similar lithographic difficulties though not to the extreme degree as seen with contacts. This study included the use of multiple, high transmission, 193nm attenuated phase shifting mask varieties to meet the difficult challenges of 65nm contact and trench lithography. Numerous illumination schemes, mask biasing, optical proximity correction (OPC), mask manufacturing techniques, and mask blank substrate materials were investigated. The analysis criteria included depth of focus, exposure latitude and MEF through pitch, reticle inspection, reticle manufacturability, and cost of ownership. The investigation determined that certain high transmission reticle schemes are strong contenders for 65nm generation contact and trench patterning. However, a number of strong interactions between illumination, OPC, and reticle manufacturing issues need to be considered.

Litho clusters with integrated metrology: the next step in continuous flow manufacturing

While integrated circuit manufacturing has demonstrated continuous productivity improvement over the last twenty years (as driven by Moores Law), there remain significant areas for improvement. The lithographic tools in current factories have set the example in productivity improvement. They have evolved from individual tools for vapor prime, coat, expose, bake operations to integrated exposure tools and photoresist tracks that handle wafers sequentially from a load port until they return to the same load port. This paper examines the next logical step in this evolution resulting in the formation of a lithography (Litho) cluster by adding metrology for critical dimension (CD) and overlay measurements and optical inspection. Since with sampling of selected sites and wafers, CD and overlay measurements are relatively quick processes, one or more lithography photocells (exposure tool and photoresist track combinations) could be integrated to one set of centrally located metrology tools. Alternatively, simpler and smaller metrology modules could be integrated into each Litho cluster tool. Since the load ports and robotics could be shared and the total number of metrology tools in the factory is expected to increase dramatically, cost reduction and economies of scale in this combination of tools may be achieved. The benefits are estimated to be a 20% improvement in cycle time and simplified material handling.

Performance of 300-mm lithography tools in a pilot production line

Semiconductor 300 is the first pilot manufacturing facility for 300mm wafers in the world. This company is a joint venture between Siemens and Motorola, formed for the purpose of developing a 300mm manufacturing tool set. The pilot line contains a full compliment of tools for DRAM manufacturing. This paper discusses the performance of the initial 300mm lithography tool set installed in our pilot line in Dresden, Germany. The product used for evaluating and debugging the tool set is a 0.25-micron ground rule 64 Meg DRAM. This was chosen for the ability to easily benchmark against 200mm DRAM manufacturing data. We have produced several lots of wafers with measurable yield. These lots have produced data on overlay, CD and run to run performance of the lithography tools on actual product. We have data on resist coating, and develop uniformity. With several lithography tools installed we have generated a large amount of mix and match data. In addition several challenges for successful lithography have surfaced related entirely to the increase in wafer size. Film, etch, polish and thermal non-uniformity have impacted the throughput and performance of the lithography tools. The installation of the first integrated 300mm pilot line has also produced data on the impact larger wafer size has on tool logistics, for example fab layout, installation schedules and wafer and lot transport. While technical data is always important, the main reason for converting to 300mm is economic. We now have preliminary data on the comparison of 200 tools to 300mm tools in terms of footprint, throughput, and productivity gains for equivalent square centimeters of silicon. With this data we can start to make preliminary recommendations for 300mm manufacturing tools.

Manufacturability of subwavelength features using reticle and substrate enhancements

This paper uses simulation and experiment to study near resolution limit patterning of contacts and damascene trenches using conventional i-line lithography. Special attention is paid to the requirements for substrate control. The patterning behavior is compared to DUV lithography results. We also evaluate the cost-of-process for an i-line process using substrate and optical enhancements compared to a standard 248 nm DUV process.

Full-field CD control for sub-0.20-μm patterning

DUV scanning exposure systems have been steadily gaining market acceptance for the past five years, and soon, all major suppliers will offer 248-nm scanning tools. One of the major reasons for the emergence of this technology has been the purported improvement in critical dimension (CD) uniformity across the scanned field versus what can be realized in a full field stepper. Using high precision electrical resistance CD metrology, we have characterized the across field CD control capability of several DUV scanning tools and DUV steppers. Analysis is carried out through focus for multiple linetypes representing various orientations and nearest-neighbor proximities. Where possible, different NA/(sigma) combinations are examined as well. Surprisingly good full field sub-0.20 micrometers CD control is obtained even for 0.50 NA, and higher NA allows for non zero process latitude at 0.14 micrometers geometries. While it was initially anticipated that 193 nm ArF lithography would be required for 0.18 micrometers technology manufacturing, it has become apparent that 248 nm lithography will be employed for these groundrules, particularly for logic applications with predominantly semi-isolated features.

Advanced 193 tri-tone EAPSM (9%-18%) for 65 nm node

Semiconductor manufacturers are increasingly focusing on contact and via layers as the most difficult lithography pattern. Focus and exposure latitude, MEF, as well as iso-dense bias are challenges for contact patterning. This situation is only expected to worsen for the 65nm device generation where the 2001 SIA roadmap update lists the contact size as 90-100nm in 2004-2005. Thus, new contact pattern techniques with novel manufacturability are required. One possible avenue to meet these stringent process control requirements is the use of tri-tone high transmission attenuated phase shifting masks (tri-tone AttPSM) for the 65nm generation. Multilayered SiN/TiN (9%-18%) EAPSM materials to manufacture advanced reticles were used in this investigation. Extensive study during the photomask processing (Front End and Back End) to access any issues related to the making of High %T tri-tone product types was performed. Finally, the 2 prototype reticles were evaluated on a 193nm scanner (0.75NA) with various illumination settings to generate imaging to support the 65nm node technology generation.

ArF (193-nm) alternating aperture PSM quartz defect repair and printability for 100-nm node

Repair and printability of 193nm alternating aperture phase shift masks have been studied in detail in an effort to understand the overall production capability of these masks for wafer production at the 100nm node and below.

Model based lithographic tool choices for a continuous state-of-the-art factory

Abstract Traditional methods of making tool selections for semiconductor manufacturing facilities tend to focus on minimizing equipment capital costs or minimizing wafer costs. A model that comprehends the effects of tool performance, product specifications, processing costs, and die yield to analyze alternate tooling strategies for lithography exposure equipment has been developed. This model enables the investigation of the profit implications of a given tool strategy. The economic framework for this model is reviewed, as are the inputs required for the lithography-specific implementation. Generalized specifications are developed for some generic I-line and DUV tools, and a process flow is defined for a generic logic device. The model is then applied using two types of analysis. The first application quantifies the differences in fab costs for several altermate tool selections. The second application investigates several multi-year tooling strategies.