Sangwoo Pae

High performance 32nm logic technology featuring 2 nd generation high-k + metal gate transistors

A 32nm logic technology for high performance microprocessors is described. 2nd generation high-k + metal gate transistors provide record drive currents at the tightest gate pitch reported for any 32nm or 28nm logic technology. NMOS drive currents are 1.62mA/um Idsat and 0.231mA/um Idlin at 1.0V and 100nA/um Ioff. PMOS drive currents are 1.37mA/um Idsat and 0.240mA/um Idlin at 1.0V and 100nA/um Ioff. The impact of SRAM cell and array size on Vccmin is reported.

BTI reliability of 45 nm high-K + metal-gate process technology

In this paper, bias-temperature instability (BTI) characterization on 45nm high-K + metal-gate (HK+MG) transistors is presented and degradation mechanism is discussed. Transistors with an unoptimized HK film stack in the early development phase exhibited pre-existing traps and large amount of hysteresis that was consistent with literature. The optimized and final HK process demonstrated NMOS and PMOS BTI on HK+MG transistors that are better than that of SiON at matched E-fields and comparable at targeted 30% higher use fields. The final process also showed no hysteresis due to fast traps thereby allowing us to characterize its intrinsic degradation mechanism. On the optimized process, NMOS BTI is attributed primarily to electron trapping in the HK bulk and HK/SiON interfacial layer (IL) regions. PMOS BTI degradation, on the other hand, is mainly interface driven and is found to be very similar to that observed on conventional SiON transistors.

Effect of BTI Degradation on Transistor Variability in Advanced Semiconductor Technologies

The effect of PMOS transistor negative bias temperature instability (NBTI) on product performance is a key reliability concern. As technology scales and device dimensions shrink, the trend in the V T variability at both time zero and after NBTI aging increases. The time0 V T variability can be explained by the random nature of dopants, whereas the randomly generated defects in the gate oxide can account for the aging-induced device DeltaV T variability. This paper focuses on the bias temperature instability stress-induced device DeltaV T variability and the trend across several technology generations. The remarkable correlation of aging-induced DeltaV T variability to the gate oxide area suggests that the continued device geometry scaling will increase the aging-induced variability. For the first time, aging-induced DeltaV T variability was characterized on transistors fabricated with high-kappa gate dielectric that also showed similar dependence to the gate oxide area.

Random charge effects for PMOS NBTI in ultra-small gate area devices

PMOS transistor degradation due to negative bias temperature instability (NBTI) has been shown to be a major transistor reliability mechanism. The effect of PMOS NBTI on the minimum operating voltage of a cache cell (Vmin) has been recently demonstrated, and the modeling of the degradation of ultra small gate area devices is vital for the accurate modeling of Vmin. Recent data and simulation has indicated that random fluctuations in device degradation are present under stress. This paper examines the source of these random fluctuations in device degradation due to PMOS NBTI.

Frequency and recovery effects in high-κ BTI degradation

Net end-of-life aging prediction under realistic use conditions is the key objective for any product aging model. In this paper, a net degradation model is introduced and effects such as recovery, subsequent degradation, frequency, duty cycle, and recovery bias are evaluated. The high-κ recovery behavior observed is consistent with SiO2 gate stacks, which allows the use of SiO2 models to predict recovery in both NMOS and PMOS high-κ transistors.

Dielectric breakdown in a 45 nm high-k/metal gate process technology

In this paper, we present extensive breakdown results on our 45nm HK+MG technology. Polarity dependent breakdown and SILC degradation mechanisms have been identified and are attributed gate and substrate injection effects. Processing conditions were optimized to achieve comparable TDDB lifetimes on HK+MG structures at 30% higher E-fields than SiON with a reduction in SILC growth. Extensive long-term stress data collection results and a change in voltage acceleration are reported.

Characterization of SILC and its end-of-life reliability assessment on 45NM high-K and metal-gate technology

Stress Induced Leakage Current (SILC) has been observed on non-optimized high-K (HK) and metal-gate (MG) transistors. Large NMOS PBTI degradation and correlation to SILC increase on such gate stack is a result of large trap generations in the bulk-HK. This poses a long term reliability concern on product standby power and can limit the operating voltage if not suppressed. On an optimized HK+MG process, we demonstrate that SILC has been suppressed. The transistor level SILC data, model and Product burn-in stress data support this. With optimized process, SILC has no impact on products made of 45nm HK+MG transistors.

Effect of NBTI degradation on transistor variability in advanced technologies

The effect of PMOS Negative Bias Temperature Instability (NBTI) on product performance is a concern. As technology scales and device dimension shrinks, the trend in the Vt-variability at both time zero and after NBTI aging increases. The timeO Vt- variability can be explained by the random nature of dopants, whereas the randomly generated defects in the gate oxide can account for the device aging-induced variability. This paper focuses on the NBTI-induced device Vt-variability and trend across technology generations. The remarkable correlation of aging-induced Vt-variability to the gate oxide area suggests that the geometry scaling is the dominant component that drives the increased trend in aging-induced variability.

PMOS NBTI-induced circuit mismatch in advanced technologies

PMOS transistor degradation due to Negative Bias Temperature Instability (NBTI) has proven to be a significant concern to present CMOS technologies. This is of particular concern for analog applications where the ability to match device characteristics to a high precision is critical. Analog circuits use larger than minimum device dimensions to minimize the effects of process variation, leaving PMOS NBTI as a possible performance limiter. This paper examines the effect of PMOS NBTI induced mismatch on analog circuits in a 90nm technology.

Gate dielectric TDDB characterizations of advanced High-k and metal-gate CMOS logic transistor technology

Transition into High-K (HK) dielectric and Metal-Gate (MG) in advanced logic process has enabled continued technology scaling in support of Moores law [1-2]. With this, CMOS operating fields have been increasing along with gate dielectric TDDB voltage acceleration factors (VAF). VAF is the most critical reliability parameter used to accurately predict the Gate oxide lifetime (TDDB) at use. This paper highlights low voltage (low-V) TDDB data is critical for the accurate assessment of HK+MG VAF and provides further evidences from both transistor- and product-level data based on 32nm technology generations.