John P. Keane

Background interstage gain calibration technique for pipelined ADCs

A mathematical framework for the convergence analysis of a pipelined ADC with background gain calibration is presented. The constraints on adaptation step size for mean convergence, for mean-squared convergence, and for signal-to-adaptation-noise ratio are derived. Furthermore, expressions for steady-state tap noise and for signal-to-adaptation-noise ratio are derived. The analysis results are verified with simulations.

Miller compensation using current buffers in fully differential CMOS two-stage operational amplifiers

Several Miller compensation schemes using a current buffer in series with the compensation capacitor to modify the right-half-plane zero in fully differential two-stage CMOS operational amplifiers are analyzed. One scheme uses a current mirror as a current buffer, while the rest use a common-gate transistor as a current buffer. The gain transfer functions are derived for each topology, and approximate transfer-function coefficients are found that allow accurate estimation of the zero(s) and poles.

Digital background calibration for memory effects in pipelined analog-to-digital converters

Memory errors can occur in the stages of a pipelined analog-to-digital converter (ADC) due to several effects. These include capacitor dielectric absorption/relaxation, incomplete stage reset at high clock rates, and parasitic capacitance effects when opamps are shared between subsequent pipeline stages. This paper describes these sources of memory errors and the effect they have on overall ADC linearity. It is shown how these errors relate to and differ from interstage gain errors. Two new calibration algorithms are proposed that correct for memory errors by digital post-processing of the ADC output. Both algorithms operate in the background and so do not require conversion to be interrupted in order to track changes due to temperature and supply variations. The two algorithms are compared in terms of their system costs and their dependence on input signal statistics

An adaptive analog noise-predictive decision-feedback equalizer

This paper describes an adaptive analog noise-predictive decision-feedback equalizer (NPDFE). It consists of an analog finite-impulse response (FIR) forward equalizer (FE), a recursive analog equalizer for noise prediction, and a decision-feedback equalizer (DFE) that uses erasure. All three analog equalizers are adaptive. Area and power are saved by using analog rather than digital equalizers because a highspeed ADC is not required and the analog equalizers used in this prototype are smaller than their digital counterparts. To demonstrate the feasibility of our proposed NPDFE, the prototype was designed for use in a disk-drive read channel.

An adaptive DFE using an IIR feedback equalizer for 100Base-TX Ethernet

An adaptive decision-feedback equalizer (DFE) that uses an infinite impulse response (IIR) feedback equalizer is presented. The target application is 100Base-TX Ethernet. Initially, a simple single pole feedback equalizer is considered. Then pole/zero feedback equalizers are considered. Simulation results are presented that compare the performance of these architectures.

Convergence analysis of a background interstage gain calibration technique for pipelined ADCs

A background self-calibration technique is proposed that can correct both linear and nonlinear errors in the interstage amplifiers of pipeline and algorithmic analog-to-digital converters (ADCs). Stage redundancy in a pipeline architecture is exploited to measure gain errors that are corrected using digital post-processing. The proposed technique allows faster convergence and has less dependence on input signal statistics than a similar technique described by Murmann and Boser. Simulation results are presented for a 12-bit pipelined ADC architecture, similar to that described by Murmann and Boser, using nonideal interstage residue amplifiers. With calibration, the simulations show a signal-to-noise-and-distortion-ratio performance of 72 dB and a spurious-free dynamic range performance of 112 dB, with calibration tracking time constants of approximately 8/spl times/10/sup 5/ sample periods, which is over ten times faster than that reported by Murmann and Boser at a similar performance level.

An Integrator-Based Pipelined ADC With Digital Calibration

A 12-bit pipelined analog-to-digital converter (ADC) uses a first-stage integrator-based open-loop residue amplifier and integrator nonlinearities are foreground calibrated. In the remaining traditional closed-loop stages, gain errors and memory errors are background calibrated. Separate reference voltages are used in the first three ADC stages to reduce interstage coupling. A 0.25-μm CMOS prototype dissipates 140 mW and occupies an active area of 5 mm2. At 40 megasamples/s (40 MS/s), the calibration improves the spurious-free dynamic range from 51.2 to 95.1 dB and the signal-to-noise-plus-distortion ratio from 43.7 to 69.0 dB.

Timing recovery for the magnetic recording channel using the wave difference method

Timing recovery using the wave difference method is proposed for use in a magnetic recording read channel. The scheme uses an oversampling ratio of two and is suitable for mixed-signal or digital implementations. A simple class of prefilter that significantly improves the signal-to-interference ratio of the generated timing-error estimate is described. This prefilter also allows a simple implementation based on an absolute value, rather than squaring or fourth-order nonlinearity. Simulation results for this scheme are presented for a range of recording densities and channel noise levels.

Analog timing recovery for a noise-predictive decision-feedback equalizer

A timing recovery architecture and its CMOS implementation are described for a noise-predictive decision-feedback equalizer (NPDFE). The 0.5-/spl mu/m CMOS prototype includes timing recovery and the NPDFE and operates at 160 Mbit/s. The timing recovery blocks dissipate 27 mW from 3.3 V, occupy 0.2 mm/sup 2/, and achieve a root mean square jitter of 50 ps, which is 0.8% of a bit period.