Kenneth C. Dyer

A digital background calibration technique for time-interleaved analog-to-digital converters

A 10-bit 40-Msample/s two-channel parallel pipelined ADC with monolithic digital background calibration has been designed and fabricated in a 1 /spl mu/m CMOS technology. Adaptive signal processing and extra resolution in each channel are used to carry out digital background calibration. Test results show that the ADC achieves a signal-to-noise-and-distortion ratio of 55 dB for a 0.8-MHz sinusoidal input, a peak integral nonlinearity of 0.34 LSB, and a peak differential nonlinearity of 0.14 LSB, both at a 10-bit level. The active area is 42 mm/sup 2/, and the power dissipation is 565 mW from a 5 V supply.

Miller compensation using current buffers in fully differential CMOS two-stage operational amplifiers

Several Miller compensation schemes using a current buffer in series with the compensation capacitor to modify the right-half-plane zero in fully differential two-stage CMOS operational amplifiers are analyzed. One scheme uses a current mirror as a current buffer, while the rest use a common-gate transistor as a current buffer. The gain transfer functions are derived for each topology, and approximate transfer-function coefficients are found that allow accurate estimation of the zero(s) and poles.

A second-order double-sampled delta-sigma modulator using additive-error switching

A second-order double-sampled delta-sigma modulator is described. It uses an additive-error switching scheme to convert capacitor mismatch into an additive out-of-band tone that can be removed by a digital filter. With a sampling rate of 5 MHz and an oversampling ratio of 256, the maximum measured signal-to-noise-and-distortion ratio (SNDR) is 86.3 dB, and the total harmonic distortion is -88.7 dB when the input is 2 dB below full scale. The modulator is fully differential, occupies 5 mm/sup 2/, and dissipates 13 mW.

Analog background calibration of a 10 b 40 Msample/s parallel pipelined ADC

The sampling rate of an ADC often limits speed of a signal processing system. Sampling rate at the A/D interface can be increased by using multiple component ADCs that are time interleaved. Mismatches in offsets, gains, and sampling times among the component ADCs limit the performance of the ADC system. Previous time-interleaved ADC arrays use careful layout, foreground calibration and/or digital filters to minimize the effects of these mismatches. The presented time-interleaved ADC uses monolithic analog background calibration to match the gains and offsets of the component pipelined ADCs. The contributions are an expandible adaptive background calibration technique for parallel ADCs and a calibration loop that uses a mixed-signal integrator. The fully-differential prototype is fabricated in a 1.0 /spl mu/m CMOS single-poly process with poly-thin-oxide-diffusion capacitors. It includes 3 pipelined ADCs, one algorithmic ADC, the calibration signal generator, channel control logic, and 6 mixed-signal integrators, each followed by a unity-gain buffer that supplies the offset or reference correction voltage to one of the pipelined ADCs. The SC integrator and ADC stages use telescopic opamps with source followers at the input.

Digital background calibration of a 10 b 40 M sample/s parallel pipelined ADC

This time-interleaved pipelined ADC uses monolithic digital background calibration to overcome the effects of the offset and gain mismatches between channels. The contributions here are use of digital background calibration to overcome these mismatches and implementation of these techniques in conjunction with the ADCs on one CMOS IC. Background calibration is done by adding a calibration signal to the ADC input and processing both simultaneously. A potential advantage of this approach is that the calibration signal acts as dither and improves the linearity of the system.

A second-order double-sampled delta-sigma modulator

A second-order double-sampled delta-sigma modulator (DSM) is described. It uses an additive-error switching scheme to convert capacitor mismatch into an additive out-of-band tone that can be removed by a digital filter. At a clock rate of 1.25 MHz and with an oversampling ratio of 256, the maximum measured signal-to-noise-and-distortion ratio is 89.8 dB, and the THD is -96.6 dB when the input is 2 dB below full scale. The modulator is fully differential, occupies 5 mm/sup 2/, and dissipates 13 mW.

An analog DFE for disk drives using a mixed-signal integrator

Intersymbol interference (ISI) limits the density in modern disk-drive systems. A forward equalizer (FE) used in conjunction with a decision-feedback equalizer (DFE) can effectively remove ISI. The functional blocks shown are: a low-noise preamp and automatic gain control (AGC), band-limiting low-pass filter (LPF), timing recovery, FE and DFE. The FE removes precursor ISI. The remaining postcursor ISI is removed by the DFE. Assuming the past decisions are correct, the DFE cancels ISI without noise enhancement. This paper describes an analog DFE. Area and power are saved by using analog rather a digital equalizers because a 6-b high-speed ADC is not required and a small analog FE can be used instead of a digital FE. The key component to realizing the analog DFE in a small area is a mixed-signal integrator.