John P. Knight

Force-directed scheduling for the behavioral synthesis of ASICs

A general scheduling methodology is presented that can be integrated into specialized or general-purpose high-level synthesis systems. An initial version of the force-directed scheduling algorithm at the heart of this methodology was originally presented by the authors in 1987. The latest implementation of the logarithm introduced here reduces the number of functional units, storage units, and buses required by balancing the concurrency of operations assigned to them. The algorithm supports a comprehensive set of constraint types and scheduling modes. These include multicycle and chained operations; mutually exclusive operations; scheduling under fixed global timing constraints with minimization of functional unit costs, minimization of register costs, and minimization of global interconnect requirements; scheduling with local time constraints (on operation pairs); scheduling under fixed hardware resource constraints; functional pipelining; and structural pipeline (use of pipeline functional units). Examples from current literature, one of which was chosen as a benchmark for the 1988 High-Level Synthesis Workshop, are used to illustrate the effectiveness of the approach. >

Scheduling and Binding Algorithms for High-Level Synthesis

New algorithms for high-level synthesis are presented. The first performs scheduling under hardware resource constraints and improves on commonly used list scheduling techniques by making use of a global priority function. A new design-space exploration technique, which combines this algorithm with an existing one based on time constraints, is also presented. A second algorithm is used for register and bus allocation to satisfy two criteria: the minimization of interconnect costs as well as the final register (bus) cost. A clique partitioning approach is used where the clique graph is pruned using interconnect affinities between register (bus) pairs. Examples from current literature were chosen to illustrate the algorithms and to compare them with four existing systems.

Power-Profiler: Optimizing ASICs Power Consumption at the Behavioral Level

This paper presents a methodology and tool (Power-Profiler) for the optimization of average and peak power consumption in the behavioral synthesis of ASICs. It considers lowering operating voltages, disabling the clock of components not in use, and architectural trade-offs, while also keeping silicon area at reasonable sizes. By attacking the power problem from the behavioral level, it can exploit an applications inherent parallelism to meet the desired performance and compensate for slower and less power-hungry operators.

Algorithms for high-level synthesis

Synthesis algorithms that offer a technique for scheduling operations and allocating registers and buses in light of both timing constraints and available hardware resources are presented. They enhance current scheduling techniques by using a global priority function that minimizes storage, interconnections, and functional unit cost. Algorithms for allocating registers and buses minimize storage and interconnection costs and take into account the interdependence of both tasks. The algorithms are also applicable to more than one method of synthesis; although first implemented in the HAL system, they have since been integrated into more specialized high-level synthesis systems.<<ETX>>

Performing scheduling and storage optimization simultaneously using genetic algorithms

This paper presents a method for performing scheduling and allocation of functional units simultaneously with storage optimization in high-level synthesis using genetic algorithms. The method involves augmenting a standard CDFG with storage operations and scheduling these operations on available storage units. The resulting synthesis tool is flexible and can support any type of storage unit from registers, to multi-port register files and memories. Results on typical circuits and benchmarks prove the flexibility and performance of this technique.

High-level synthesis of digital circuits using genetic algorithms

Describes a high-level synthesis system that uses genetic algorithms (GAs). The use of GAs allows for a synthesis method that is more flexible and more adaptable to new constraints than the traditional heuristic and integer linear programming approaches. The proposed GA tool is suitable for large, realistic problems. It performs simultaneous scheduling, allocation and binding of functional and storage units minimizing multiple related performance constraints such as latency, area throughput and power. The synthesis tool is capable of performing with control/data flow graphs.

Applicability of a Subset of Ada as an Algorithmic Hardware Description Language for Graph-Based Hardware Compilation

The requirements of an algorithmic level hardware description language can be met by a software language with only limited feature enhancement. This paper discusses the feasibility of using a subset of Ada as a hardware description language. Methods are presented for realizing the extra features required for hardware description within the syntax of Ada. This allows the compiled Ada program to act as a functional simulator. Our particular context for hardware description is as a source language for a hardware compiler. Rules are presented for translating a circuit described in the Ada subset onto a control/data-flow graph (CDFG), our intermediate level form.

Concurrent testing in high-level synthesis

For digital circuits synthesized from data-flow graphs, this paper presents a method to test the circuit concurrently with its normal operation. The method tests hardware elements when they are not in use in the data-flow graph. An algorithm for synthesizing the test circuit is presented that starts with the data-flow graph, generating a circuit to cycle test vectors through the idle hardware and produce a signature so as to give a built-in-self-test. By utilizing idle computational time for testing, the method reduces test-time overheads.<<ETX>>

PASSOS: a different approach for assignment and scheduling for power, area and speed optimization in high-level synthesis

This paper presents a high-level (behavioral) synthesis method that takes advantage of digit-serial arithmetic to minimize power consumption, transistor counts and delays. Genetic algorithms are used for simultaneous scheduling and assignment to obtain significant savings and improvements compared with parallel (32-bit) implementations and/or the best results reported in the literature.

Operations research in the high-level synthesis of integrated circuits

Abstract The acceptance of high-level synthesis tools and methodologies by the design engineers depends on their efficiency in producing circuits with small silicon areas and high operating speeds. This paper shows how this efficiency can be achieved through the use of several operations research techniques applied to the many optimization problems that must be solved. These include: shortest path algorithms, integer programming techniques applied to silicon area minimization, force directed scheduling to optimize the number of operators and cost/speed trade-offs of logical gates. This paper presents several examples providing an operations research solution to each of them.