Norman M. Filiol

An agile ISM band frequency synthesizer with built-in GMSK data modulation

In this paper, a high-resolution fractional-N RF frequency synthesizer is presented which is controlled by a fourth-order digital sigma-delta modulator. The high resolution allows the synthesizer to be digitally modulated directly at RF. A simplified digital filter which makes use of sigma-delta quantized tap coefficients is included which provides built-in GMSK pulse shaping for data transmission. Quantization of the tap coefficients to single-bit values not only simplifies the filter architecture, but the fourth-order digital sigma-delta modulator as well. The synthesizer makes extensive use of custom VLSI, with only a simple off-chip loop filter and VCO required. The synthesizer operates from a single 3-V supply, and has low power consumption. Phase noise levels are less than -90 dBc/Hz at frequency offsets within the loop bandwidth. Spurious components are less than -90 dBc/Hz over a 19.6-MHz tuning range.

Design and realization of a digital /spl Delta//spl Sigma/ modulator for fractional-n frequency synthesis

The basic operation of a fractional-n frequency synthesizer has been published, but to date little has been presented on the digital /spl Delta//spl Sigma/ modulators which are required to drive such synthesizers. This paper provides a tutorial overview, which relates digital /spl Delta//spl Sigma/ modulation to other applications of /spl Delta//spl Sigma/ modulation where the literature is more complete. The paper then presents a digital /spl Delta//spl Sigma/ modulator architecture which is economical and efficient and which is practical to realize with commercially available components in comparison with other possible implementations which require extensive custom very large-scale integration (VLSI). A demonstration is made of a 28-b modulator using the architecture presented, which provides a 25-MHz tuning bandwidth and <1-Hz frequency resolution. The modulator is demonstrated in an 800-MHz frequency synthesizer having phase noise of -90 dBC/Hz at a 30-kHz offset.

An interpolated frequency-hopping spread-spectrum transceiver

A technique of spread-spectrum transmission, interpolated frequency-hopping (IFH), is presented. IFH employs a carrier that moves smoothly and continuously in frequency, helping to alleviate problems, such as spectral splatter and transient mismatch, which are a concern in conventional phase-locked loop (PLL)-based frequency-hopping spread-spectrum systems. In IFH, the pseudorandom hopping code is passed through a digital interpolation filter prior to controlling the synthesizer instantaneous frequency output. While such filtering is commonly used in data pulse-shaping to improve the spectral characteristics of the modulated carrier, such filtering has not been reported for IFH codes, where the frequency deviations are changing and can span several MHz. The implications of matching the transient responses of two PLL-based frequency synthesizers using this method have also not been reported. Initial simulation and laboratory measurements indicate that, for certain cases, IFH shows a 1.9 dB improvement in received IF power, has a much sharper roll-off of inband phase noise when compared to conventional hopping, and provides a phase-coherent IF after despreading. An IFH transceiver system using /spl Delta/-/spl Sigma/ frequency synthesis and a /spl Delta/-/spl Sigma/ frequency discriminator is proposed. The system would be suitable for integrated mobile radio applications in slow-fading environments.

A 0.009–1.4-GHz Frequency Synthesizer With Suppressed Transients During VCO Band Switching

This brief presents a 0.009-1.4-GHz frequency synthesizer that is able to compensate for changes in the frequency tuning range, due to temperature variations, by switching voltage-controlled oscillator (VCO) bands with minimal phase and frequency errors, without cycle slipping and without introducing any phase offsets. This is accomplished by a subthreshold capacitor bank switching circuit that causes the gradual addition of capacitance slowly enough to allow the loop to adjust the VCO control voltage to compensate. The additional circuitry uses less than 0.001 mm2 of silicon area and has minimal power consumption and minimal effects on the synthesizers phase noise when fully switched. The synthesizer used to demonstrate this was implemented in a 0.18-μm SiGe BiCMOS process and achieves 365-fs integrated jitter at 1.05 GHz, with a total power consumption of 81 mW. Measurements of the capacitor bank switching circuit shows that it prevents cycle slipping during band switching and reduces the maximum frequency deviation by 99.3%.

Digitally Place and Routed Up-converting Bandpass DAC

By manipulating digital tools to include a single analog cell, the complete DAC and IF transmit path of a radio is automatically placed and routed in 0.12 mm2. Implemented in 0.18 mum CMOS, an over-sampled SigmaDelta modulator quantizes the data stream and a semi-analog filter selects a replica of the desired signal at IF. Based on instances of a 5-transistor analog cell, an integrated mixed-signal filter picks off the desired replica, filters the quantization noise, and delivers an analog IF output. Transmitting at an IF of 192 MHz, measurements confirm that the DAC, mixer and filter have a bandwidth of 3.2 MHz, 12-bit linearity and consume 32 mW. Despite automated layout, the circuit consumes less than 1/10th the area and 1/6th the power of custom up-converting designs. The area, power, bandwidth and output frequency are a function of the digital modulator, and scale with technology

A receive path /spl Delta//spl Sigma/ frequency to digital converter

In this paper a novel architecture for a second order /spl Delta//spl Sigma/ frequency-to-digital converter (FDC), aimed at receive path applications, is presented. The new architecture uses fractional-N division techniques in order to reduce the fullscale input range and out of band quantization noise when used to detect small deviation FM signals, relative to the reference frequency. The output is a single bit bitstream whose average density is an accurate representation of the instantaneous frequency deviations of the modulated IF signal.

A two-loop third-order multistage /spl Delta//spl Sigma/ frequency to digital converter

This paper presents a /spl Delta//spl Sigma/ frequency to digital converter based on two /spl Delta//spl Sigma/ phase-locked loops (PLLs). A primary /spl Delta//spl Sigma/ PLL performs frequency discrimination with first order noise shaping while a secondary /spl Delta//spl Sigma/ PLL performs a second order noise shaped measurement of the quantization phase error introduced by the primary PLL. Then, as in multistage A/D converters, the two digital outputs are combined to produce a cancellation of the quantization error introduced by the primary PLL . This paper presents results from a hardware prototype following the above concept, built with discrete ECL components. Measured results indicate that the circuit could function as a highly linear FM demodulator from an IF frequency or alternatively could form part of a frequency synthesizer. The secondary /spl Delta//spl Sigma/ PLL which provides a noise shaped phase error to digital conversion appears to be new. Its application to frequency synthesis is also discussed.