John P. Mack

Integrated Photonics for Low-Power Packet Networking

Communications interconnects and networks will continue to play a large role in contributing to the global carbon footprint, especially in data center and cloud-computing applications exponential growth in capacity. Key to maximizing the benefits of photonics technology is highly functional, lower power, and large-scale photonics integration. In this paper, we report on the latest advances in the photonic integration technologies used for asynchronous optical packet switching using an example photonic integrated switched optical router, the label switched optical router architecture. We report measurements of the power consumed by the photonic circuits in performing their intended function, the electronics required to bias the photonics, processing electronics, and required cooling technology. Data is presented to show that there is room (potentially greater than 10 ×) for improvement in the router packet-forwarding plane. The purpose of this exercise is not to provide a comparison of all-optical versus electronic routers, rather to present a data point on actual measurements of the power contributions for various photonic integration technologies of an all-optical packet router that has been demonstrated and conclude, where the technology can move to reduce power consumption for high-capacity packet routing systems.

Photonic integrated circuit optical buffer for packet-switched networks

A chip-scale optical buffer performs autonomous contention resolution for 40-byte packets with 99% packet recovery. The buffer consists of a fast, InP-based 2 x 2 optical switch and a silica-on-silicon low loss delay loop. The buffer is demonstrated in recirculating operation, but may be reconfigured in feed-forward operation for longer packet lengths. The recirculating buffer provides packet storage in integer multiples of the delay length of 12.86 ns up to 64.3 ns with 98% packet recovery. The buffer is used to resolve contention between two 40 Gb/s packet streams using multiple photonic chip optical buffers.

SOA Gate Array Recirculating Buffer for Optical Packet Switching

A compact recirculating buffer using an InP-based 2×2 switch with gain and a fiber delay line is demonstrated at 40 Gb/s. Packet throughput of 98% is measured for up to 8 circulations, or 0.18 μs.

SOA gate array recirculating buffer with fiber delay loop.

We present a compact variable delay buffer for storage of 40 byte packets. The recirculating buffer is based on an InP SOA gate array two-by-two switch which provides greater than 40 dB of extinction, sub-nanosecond switching, and fiber-to-fiber gain. The switch is used with a fiber delay loop 450 centimeters, or 23 ns, in length. The buffer is demonstrated with greater than 98% packet recovery at 40 Gb/s for up to 184 ns of storage.

Variable Length Optical Packet Synchronizer

Synchronization of asynchronously arriving variable length Internet Protocol packets to a local clock is demonstrated using a fiber-based optical synchronizer. The synchronizer is a four-stage feed-forward design with a resolution of 853 ps and a dynamic tuning range of 12.8 ns. The arrival time of packets is determined on a per packet basis using a payload envelope detection technique. The synchronizer state is dynamically configured on a per packet basis determined from the arrival time. Layer-1 (bit-error-rate) measurements are presented with power penalties 0.5 dB and an input power dynamic range 15 dB. Layer-2 (packet recovery) measurements are presented with power penalties 1.5 dB.

40 Gb/s Autonomous Optical Packet Synchronizer

We demonstrate a 40Gb/s autonomous optical packet synchronizer with a resolution of 853ps and dynamic tuning range of 12.8ns. Layer-1 (BER) and Layer-2 (Packet Recovery) measurements are presented with > 15dB input power dynamic range.

Synchronously Loaded Optical Packet Buffer

Synchronous optical packet buffering is demonstrated utilizing a fiber-based synchronizer with a photonic integrated circuit packet buffer. Asynchronously arriving packets are optically synchronized to a local frame clock and loaded synchronously into the optical buffer. The synchronizer is a four-stage design with a resolution of 853 ps and a dynamic tuning range of 12.8 ns. The optical packet buffer consists of an integrated 2 × 2 InP switch coupled to a silica-on-silicon 12.8-ns delay line. Packet recovery measurements of 40-B return-to-zero packets at 40 Gb/s show-error free performance for several combinations of synchronizer and buffer delays.

Photonic Chip Recirculating Buffer for Optical Packet Switching

The first on-chip optical buffer is demonstrated with up to 64 ns of delay with 98% packet recovery. The recirculating buffer is implemented using a fast, InP-based switch butt-coupled to a low-loss silica waveguide delay.

Photonic integrated circuit switch matrix and waveguide delay lines for optical packet synchronization

The first integrated synchronizer is demonstrated using silica delays coupled to an InP switch. Error-free performance is presented for delays of 0, 2.96, 6.56 and 9.52 ns.

Demonstration of contention resolution for labeled packets at 40 Gb/s using autonomous optical buffers

Contention resolution of labeled optical packets is demonstrated utilizing two packaged optical buffers. Forwarding and buffering decisions are autonomously determined for 40 Gb/s payloads from 10 Gb/s labels with greater than 99.9% packet recovery demonstrated.