John Reuben

Capacitance driven clock mesh synthesis to minimize skew and power dissipation

Tree driven mesh is gaining popularity as a viable method to distribute clock with minimum skew in Deep Sub Micron (DSM) technology. In the design of the leaf level mesh, the density of the mesh at various parts of the chip is a crucial factor which decides the clock skew and power dissipated in the mesh. We propose a capacitance driven mesh formation methodology which forms a minimum wire length, non-uniform mesh when compared to the traditional skewdriven mesh. After connecting the sinks to the mesh by a combination of Steiner tree and stubs, appropriately sized buffers are placed at optimal locations such that skew and power dissipation are minimized. When our algorithms were tested on ISPD2010 benchmarks, the power dissipated in the mesh was found to be 25% lesser and the skew was 32% to 45% lesser than the skew driven mesh.

Low power, high speed hybrid clock divider circuit

The Clock Divider circuit has found immense application in Multiple Clock Domain (MCD) systems like ASICs, SoC and GALS. In MCD systems, we generate many clock signals of various frequencies from a high frequency clock by frequency division. Power is an important parameter to be minimized since the nodes in a clock divider circuit will toggle at clock frequency. In this paper, we present a low power hybrid clock divider circuit which can take an input frequency up to 6 GHz and perform frequency division. The divider is hybrid because it uses two different flip flops - a Modified Extended True Single-Phase Clock flip flop (METSPC-FF) and a self blocking FF (SBFF).The METSPC-FF is fast enough to divide a GHz frequency, but consumes more power when compared to SBFF, while the SBFF is relatively slow but consumes less power compared to METSPC. We analyze the performance of these 2 FFs across PVT variations and implement them in a clock divider circuit. Our clock divider circuit consumes 149.56 µW power for ‘divide by’ 8 operation on a 6 GHz clock. Simulation of these flip flops in TSMC 90 nm technology using CADENCE SPECTRE simulator shows that they are very energy efficient and hence can be used for other high speed applications without compromising on the power.

A novel clock generation algorithm for system-on-chip based on least common multiple

Display Omitted An algorithm to generate the clocks for the different cores in a System-on-Chip (SoC) is proposed.The algorithm minimizes the number of Phase Locked Loops (PLLs) required in a SoC.As a result, the power consumed by the clock generator circuit of a SoC can be reduced.Design cost and area of a SoC can also be minimized. Due to increase in the number of Intellectual Property (IP) cores, clock generation in current day System-on-Chips (SoCs) is facing a crisis. The conventional method of using a dedicated Phase Locked Loop (PLL) to generate the clock for each IP core is becoming inefficient in terms of power and cost. We propose an algorithm based on Least Common Multiple (LCM) to minimize the number of PLLs required to generate the clocks for the IP cores in a SoC. This is done by finding an Optimum Operating Frequency (OOF) for each IP core within 10% below the maximum operating frequency of the core. The OOF is chosen such that the LCM of the OOF of all the IP cores is minimized. Simulated annealing is used to find the LCM. This LCM is the crucial high frequency from which maximum number of clocks can be derived by clock dividers.

Clock frequency doubler circuit for multiple frequencies and its application in a CDN to reduce power

The frequency doubler(FD) circuit has found immense use in digital CMOS systems. Such a circuit is especially useful in a clock distribution network where the clock signal can be distributed at a low frequency and multiplied (clock frequency made 2 or 4 times) at the blocks where a higher frequency is needed. This reduces the power consumption of the clock distribution network. Clock Frequency Multiplier circuits are also useful in chips to generate clock signals which are multiples of the available clock frequency generated by the oscillator. In this paper, we have designed a clock frequency doubler circuit suitable to reduce power consumption in a clock distribution network. The FD doubles fixed frequencies namely 250 MHz, 500MHz and 1 GHz. It also doubles frequency 10% around these fixed frequencies. The simulated circuit consumes only 411 pW of power and has a propagation delay of only 43.75nS.This circuit was then connected at the 4 leaves of a H-tree global CDN to double the clock frequency. This CDN achieved 50.2 % power savings when compared to a CDN distributing clock at the target frequency.

LOW POWER FRACTIONAL-N FREQUENCY DIVIDER WITH IMPROVED RESOLUTION

Multiple clock domain (MCD) systems have different blocks/IP cores operating at different frequencies. These different clocks are generated from a high frequency clock usually by integer division. Fractional-N frequency dividers (FFDs) are needed when the clock required by a block in MCD system is not possible to be derived by simple integer division. In this paper, we present such a FFD with an improved resolution of (1/8). Post layout simulation results after parasitic RC extraction in the 90-nm technology node show that our FFD is able to fractionally divide signals upto 2 GHz frequency with an average error of 0.11% in division ratio even with 2.5° phase error at the input. Our FFD consumes 754 μW when fractionally dividing a 2 GHz signal with a resolution of (1/8).

Buffer reduction algorithm for mesh-based clock distribution

In deep sub-micron technology, Mesh-based clock distribution is becoming a preferred method to distribute the clock since it is tolerant to process variations. Buffers are placed on the mesh nodes to drive the mesh wire capacitance and large load capacitance of clock sinks. In this short paper, we propose a buffer reduction algorithm which can reduce the power dissipated in clock meshes. We calculate the importance of each buffer by the impact its removal has on the clock latency and clock slew at sinks. We then calculate a rank for each buffer and buffers with lower ranks are removed. Our buffer reduction algorithm is able to achieve 15-18% reduction in power at the cost of 10-20 ps increase in skew when compared to the previously published work.