Harish M. Kittur

Low-Power and Area-Efficient Carry Select Adder

Carry Select Adder (CSLA) is one of the fastest adders used in many data-processing processors to perform fast arithmetic functions. From the structure of the CSLA, it is clear that there is scope for reducing the area and power consumption in the CSLA. This work uses a simple and efficient gate-level modification to significantly reduce the area and power of the CSLA. Based on this modification 8-, 16-, 32-, and 64-b square-root CSLA (SQRT CSLA) architecture have been developed and compared with the regular SQRT CSLA architecture. The proposed design has reduced area and power as compared with the regular SQRT CSLA with only a slight increase in the delay. This work evaluates the performance of the proposed designs in terms of delay, area, power, and their products by hand with logical effort and through custom design and layout in 0.18-μm CMOS process technology. The results analysis shows that the proposed CSLA structure is better than the regular SQRT CSLA.

First Principle Simulations of Various Magnetic Tunnel Junctions

This paper reports the first principle simulations of Fe/MgO/Fe, Fe/Y2O3/Fe, Fe/HfO2/Fe, and Fe/Al2O3/Fe magnetic tunnel junctions (MTJs). From the device-level and circuit-level simulations carried out in this paper, the Fe/MgO/Fe configuration has been found to be the best. From the device-level simulations, all the four configurations of MTJs have been compared with regards to the bias dependence of tunnel magnetoresistance ratios (TMRs), insulator thickness dependence of TMR, and insulator thickness dependence of parallel and antiparallel state resistances. Finally, from the circuit-level simulations, the static and switching power dissipations have been computed along with the delay time estimation.

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In System on Chip, buses and point to point links are used as a communication infrastructure between one IP to another, but these cannot provide efficient interconnect from performance point of view. So NoC architecture was proposed to provide communication in multiprocessor SoC and overcome the limitations. This paper has implemented a 5-port 32-bit and 64-bit router architecture using wormhole routing technique for 2D-mesh network by using simple deterministic algorithm, flow control and decoding mechanism. In this router, 2 types of crossbar are used named as multiplexer and tri-state buffer matrix for efficient design. Comparisons of area and power are done for these router designs using ASIC tool flow in Cadence using TSMC 90nm and 180nm process technologies. Simulation results are performed in Cadence NC simulator. It is demonstrated that multiplexer router design is more efficient than a matrix router design as area and power increases for matrix design while using same port-width.

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High gate leakage current, as a central problem, has decelerated the downscaling of minimum feature size of the field effect transistors In this paper, a combination of density functional theory and non equilibrium Green’s function formalism has been applied to the atomic scale calculation of the tunnel currents through CeO2, Y2O3, TiO2 and Al2O3 dielectrics in MOSFETs. The tunnel currents for different bias voltages applied to Si/Insulator/Si systems have been obtained along with tunnel conductance v/s bias voltage plots for each system. The results are in agreement to the use of high dielectric constant materials as gate dielectric so as to enable further downscaling of MOSFETs with reduced gate leakage currents thereby enabling ultra large scale integration. When used as dielectric, TiO2 exhibits extremely low tunnel currents followed by Y2O3 while CeO2 and Al2O3 exhibit high tunnel currents through them at certain bias voltages.

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Tree driven mesh is gaining popularity as a viable method to distribute clock with minimum skew in Deep Sub Micron (DSM) technology. In the design of the leaf level mesh, the density of the mesh at various parts of the chip is a crucial factor which decides the clock skew and power dissipated in the mesh. We propose a capacitance driven mesh formation methodology which forms a minimum wire length, non-uniform mesh when compared to the traditional skewdriven mesh. After connecting the sinks to the mesh by a combination of Steiner tree and stubs, appropriately sized buffers are placed at optimal locations such that skew and power dissipation are minimized. When our algorithms were tested on ISPD2010 benchmarks, the power dissipated in the mesh was found to be 25% lesser and the skew was 32% to 45% lesser than the skew driven mesh.

Applications in Magnetoresistive Random Access Memories

The Clock Divider circuit has found immense application in Multiple Clock Domain (MCD) systems like ASICs, SoC and GALS. In MCD systems, we generate many clock signals of various frequencies from a high frequency clock by frequency division. Power is an important parameter to be minimized since the nodes in a clock divider circuit will toggle at clock frequency. In this paper, we present a low power hybrid clock divider circuit which can take an input frequency up to 6 GHz and perform frequency division. The divider is hybrid because it uses two different flip flops - a Modified Extended True Single-Phase Clock flip flop (METSPC-FF) and a self blocking FF (SBFF).The METSPC-FF is fast enough to divide a GHz frequency, but consumes more power when compared to SBFF, while the SBFF is relatively slow but consumes less power compared to METSPC. We analyze the performance of these 2 FFs across PVT variations and implement them in a clock divider circuit. Our clock divider circuit consumes 149.56 µW power for ‘divide by’ 8 operation on a 6 GHz clock. Simulation of these flip flops in TSMC 90 nm technology using CADENCE SPECTRE simulator shows that they are very energy efficient and hence can be used for other high speed applications without compromising on the power.

Area and power efficient network on chip router architecture

Traditional fast Discrete Cosine Transforms (DCT)/ Inverse DCT (IDCT) algorithms have focused on reducing the arithmetic complexity. In this manuscript, we implemented a new architecture simultaneous for image compression and encryption technique suitable for real-time applications. Here, contrary to traditional compression algorithms, only special points of DCT outputs are calculated. For the encryption process, LFSR is used to generate random number and added to some DCT outputs. Both DCT algorithm and arithmetic operators used in algorithm are optimized in order to realize a compression with reduced operator requirements and to have a faster throughput. High Performance Multiplier (HPM) is being used for integer multiplications. Simulation results show the compression ratio around 66% and a PSNR about 24dB. The throughput of this architecture is 624 M samples/s with a clock frequency of 78 MHz.

First Principle Study of Tunnel Currents through CeO2, Y2O3, TiO2 and Al2O3 Dielectrics in MOSFETs for Ultra Large Scale Integration

Multiplication is a significant process in digital signal processing algorithms. These algorithms involve large number of multiplications, which is time consuming. In digital signal applications time is more important as compared to accuracy. In this paper a simple and efficient architecture of multiplier is proposed which uses adders, shifters, encoders and decoder etc. that consume less area, time and power. The multiplication is based on Mitchells algorithm. This multiplier gives arbitrary accuracy but with only two iterations it gives very less error that is limited to 2% which is tolerable in digital signal algorithms. This multiplier is implemented in ASIC using SOC encounter and NCSIM simulator in Cadence with 180nm technology for 16 bit operands at 12.5 MHz frequency.

Capacitance driven clock mesh synthesis to minimize skew and power dissipation

The major issue of RRAM is the uneven sneak path that limits the array size. For the first time record large One-Resistor (1R) RRAM array of 128x128 is realized, and the array cells at the worst case still have good Low-/High-Resistive State (LRS/HRS) current difference of 378 nA/16 nA, even without using the selector device. This array has extremely low read current of 9.7 μA due to both low-current RRAM device and circuit interaction, where a novel and simple scheme of a reference point by half selected cell and a differential amplifier (DA) were implemented in the circuit design.

Low power, high speed hybrid clock divider circuit

Content-addressable memory (CAM) is the hardware for parallel lookup/search. The parallel search scheme promises a high-speed search operation but at the cost of high power consumption. Parallel NOR- and NAND-type matchline (ML) CAMs are suitable for high-search-speed and low-power-consumption applications, respectively. The NOR-type ML CAM requires high power, and therefore, the reduction of its power consumption is the subject of many reported designs. Here, we report and explore the short-circuit (SC) current during the precharge phase of the NOR-type ML. Also proposed here is a novel precharge-free CAM. The proposed CAM is free of the drawbacks of the charge sharing in the NAND and the SC current in the NOR-type CAM. Postlayout simulations performed with a 45-nm technology node revealed a significant reduction in the energy metric: 93% and 77% lesser than NOR- and NAND-type CAMs, respectively. The Monte Carlo simulation for 500 runs was performed to ensure the robustness of the proposed precharge-free CAM.