John Robert Campbell
General Electric
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electronics packaging technology conference | 2004
Ananth Prabhakumar; John Robert Campbell; Ryan Rexford Mills; Paul Jeffrey Gillespie; David Richard Esler; Slawomir Rubinsztajn; Sandeep Tonapi; Krishnaswarmi Srihari
The assembly and packaging of electronic devices today is becoming increasingly challenging and demanding because of requirements for smaller, faster and lighter products that provide increasing functionality at low cost. These requirements continue to place greater demands on the electronics industry and mandate improved packaging technology. In part, flip chip packaging technology is the response to these demands and provides a solution to these challenges. While flip chip packaging provides a solution to evolving device requirements, underfill materials are required to improve flip chip device reliability. These resins overcome poor device reliability issues resulting from the mismatch of coefficient of thermal expansion (CTE) between the silicon die and the organic substrate. However, offsetting the gains in device reliability are additional processing steps that adversely affect manufacturing productivity. To compensate for this adverse effect on manufacturing productivity, several new processes, such as wafer level underfill, have been developed. In this paper, we describe the assembly and reliability of flip chips with a nanofilled wafer level underfill (WLU). This approach allows application of the underfill material on the entire wafer, such that many chips can be underfilled simultaneously. Assembly is then carried out with a compatible epoxy flux material. Air-to-air thermal shock (AATS) results and failure mechanisms are described for this novel approach
electronics packaging technology conference | 2003
Ananth Prabhakumar; Slawomir Rubinsztajn; D. Buckley; John Robert Campbell; D. Sherman; David Richard Esler; E. Fiveland; A. Chaudhuri; Sandeep Tonapi
Flip chip package design has a significant drawback related to the mismatch of coefficient of thermal expansion (CTE) between the silicon die and the organic substrate. This CTE mismatch creates stress on the solder joints during thermal excursions, which reduces the fatigue lifetime of the solder joints. This leads to premature failures of the package. However, package reliability can be improved by the application of an underfill material. In this communication, we report the development of a novel filled no-flow underfill material utilizing proprietary filler technology, which provides a previously unobtainable balance of low CTE, high glass transition temperature (Tg), and good solder joint formation. The fluxing parameters and effect of catalyst level on assembly yield are presented. Assembly results (yield, void area) are presented and compared with commercially available no-flow underfill materials.
Tetrahedron Letters | 1980
John Robert Campbell
Abstract Previously unknown diaryl-dihalomethylcarbonium ions, formed in high yield from the respective alkenes in trifluoromethanesulfonic acid (triflic acid) undergo facile rapid equilibration of aryl groups in triflic acid with a second added aryl component.
Archive | 1995
Tohru Takekoshi; Farid Fouad Khouri; John Robert Campbell; Therese Coste Jordan; Kevin Hsingtao Dai
Archive | 1999
John Robert Campbell; John J. Talley; Neal Steven Falcone; Johannes Martinus Dina Goossens; Luc Carlos Govaerts; Hendrik Verhoogt; Richard Lucas; James Ross Fishburn; Nirajkumar Patel; Matthew Ladd Reitz
Archive | 2003
Sandeep Tonapi; John Robert Campbell; Ryan Christopher Mills; Ananth Prabhakumar; Slawomir Rubinsztajn
Archive | 2003
John Robert Campbell; Slawomir Rubinsztajn; Joseph Michael Anostario
Archive | 2004
John Robert Campbell; Bryan Duffey; John Rude; Prameela Susarla; Michael Alan Vallance; Gary Williams Yeager; Kenneth Paul Zarnoch
Archive | 2004
Slawomir Rubinsztajn; John Robert Campbell; Joseph Michael Anostario; Ananth Prabhakumar; Donna Marie Sherman; Sandeep Tonapi
Archive | 2000
Padmavathy Rajagopalan; John Robert Campbell; Larry Neil Lewis