Ananth Prabhakumar

Assembly and reliability of flip chips with a nano-filled wafer level underfill

The assembly and packaging of electronic devices today is becoming increasingly challenging and demanding because of requirements for smaller, faster and lighter products that provide increasing functionality at low cost. These requirements continue to place greater demands on the electronics industry and mandate improved packaging technology. In part, flip chip packaging technology is the response to these demands and provides a solution to these challenges. While flip chip packaging provides a solution to evolving device requirements, underfill materials are required to improve flip chip device reliability. These resins overcome poor device reliability issues resulting from the mismatch of coefficient of thermal expansion (CTE) between the silicon die and the organic substrate. However, offsetting the gains in device reliability are additional processing steps that adversely affect manufacturing productivity. To compensate for this adverse effect on manufacturing productivity, several new processes, such as wafer level underfill, have been developed. In this paper, we describe the assembly and reliability of flip chips with a nanofilled wafer level underfill (WLU). This approach allows application of the underfill material on the entire wafer, such that many chips can be underfilled simultaneously. Assembly is then carried out with a compatible epoxy flux material. Air-to-air thermal shock (AATS) results and failure mechanisms are described for this novel approach

Development of no-flow underfill materials and processes for Pb-free flip chip applications

Due to pending legislation worldwide, the semiconductor packaging industry is switching over to Pb-free electronics assembly. Flip chip packaging, which is one of the fastest growing segments of packaging technology, is also affected by this trend. It is a common practice to underfill flip chip devices to compensate for the coefficient of thermal expansion (CTE) mismatch between the die and the chip carrier. However, compatible underfill materials and processes are necessary for the effective migration of flip chip packaging towards Pb-free. Among the various underfilling techniques used in the industry, the no-flow underfill (NFU) process has the potential to increase throughput and reduce manufacturing costs as stated in D. Gamota and C. Melton (1998). There has been a significant research effort within the industry to develop NFU materials and processes for eutectic applications, but Pb-free reflow temperatures pose a significant challenge to the development of a NFU that is compatible with the Pb-free assembly process. Recently, we have developed a Pb-free compatible NFU material with a combination of self fluxing capability and cure kinetics that allows for successful assembly of 95.5Sn/3.8Ag/0.7Cu bumped flip chip devices. In this paper, the effect of various process variables that affect voiding in the underfill interface is investigated. In addition to these studies, the assembly yields for a Pb-free compatible underfill used to assemble different flip chip components with 95.5Sn/3.8Ag/0.7Cu alloy are discussed

Development of a novel filled no-flow underfill material for flip chip applications

Flip chip package design has a significant drawback related to the mismatch of coefficient of thermal expansion (CTE) between the silicon die and the organic substrate. This CTE mismatch creates stress on the solder joints during thermal excursions, which reduces the fatigue lifetime of the solder joints. This leads to premature failures of the package. However, package reliability can be improved by the application of an underfill material. In this communication, we report the development of a novel filled no-flow underfill material utilizing proprietary filler technology, which provides a previously unobtainable balance of low CTE, high glass transition temperature (Tg), and good solder joint formation. The fluxing parameters and effect of catalyst level on assembly yield are presented. Assembly results (yield, void area) are presented and compared with commercially available no-flow underfill materials.

Theoretical Modeling and Prediction of Delamination in Flip Chip Assemblies With Nanofilled No-Flow Underfill Materials

The occurrence of passivation-underfill interfacial delamination is detrimental to the reliability of the flip chip assembly as it can result in the premature cracking of the solder bumps. In this paper, the propagation of delamination in a nanofilled no-flow underfill material from the chip passivation in flip chip assemblies has been assessed under accelerated thermal shock testing. A theoretical model of the flip chip assembly has been developed, and the delamination occurring at the silicon nitride (SiN)–underfill interface has been studied under monotonic as well as thermomechanical fatigue loading. Using empirical models for delamination propagation, the growth of delamination under monotonic as well as thermomechanical fatigue loading in a flip chip assembly has been predicted. These predictions agree well with the thermal shock cycling experimental data. The agreement between the theoretical predictions and experimental data suggests that the models and the methodology developed in this work can be used to design flip chip assemblies with nanofillled no-flow underfill materials against interfacial delamination.