John V. Woods

Investigation into micropipeline latch design styles

An asynchronous implementation of the ARM microprocessor has been designed and fabricated based on Sutherlands Micropipeline approach. Reviews of this work have shown that considerable performance improvement may be possible in a number of key design areas. This paper assesses the effects of different design styles on the micropipeline latch structures used. The original design has latch structures based on pass-transistor transparent latches. An evaluation of the use of single-phase transparent latch structures is given plus the application of 2-phase and 4-phase control techniques. >

Efficient modelling of spiking neural networks on a scalable chip multiprocessor

We propose a system based on the Izhikevich model running on a scalable chip multiprocessor - SpiNNaker - for large-scale spiking neural network simulation. The design takes into account the requirements for processing, storage, and communication which are essential to the efficient modelling of spiking neural networks. To gain a speedup of the processing as well as saving storage space, the Izhikevich model is implemented in 16-bit fixed-point arithmetic. An approach based on using two scaling factors is developed, making the precision comparable to the original. With the two scaling factors scheme, all of the firing patterns by the original model can be reproduced with a much faster execution speed. To reduce the communication overhead, rather than sending synaptic weights on communicating, we only send out event packets to indicate the neuron firings while holding the synaptic weights in the memory of the post-synaptic neurons, which is so-called event-driven algorithm. The communication based on event packets can be handled efficiently by the multicast system supported by the SpiNNaker machine. We also describe a system level model for spiking neural network simulation based on the schemes above. The model has been functionally verified and experimental results are included. An analysis of the performance of the whole system is presented at the end of the paper.

AMULET1: a micropipelined ARM

A fully asynchronous implementation of the ARM microprocessor has been developed in order to investigate the potential of asynchronous logic for low-power applications. The work demonstrates the feasibility of complex asynchronous design and shows that the cost and performance characteristics are similar to clocked designs. AMULET1 is the first attempt at applying asynchronous techniques to a design of this complexity and as such there is much room for improvement. The authors introduce the design approach and organisation of the chip; they then cover the lessons learned from the first design and point towards future strategies for its enhancement and the likely benefits which will accrue from mature asynchronous technology.<<ETX>>

AMULET3i-an asynchronous system-on-chip

AMULET3i is the third generation asynchronous ARM-compatible microprocessor subsystem developed at the University of Manchester. It is internally modular being based around the MARBLE asynchronous on-chip bus, and is also extensible through the addition of conventional clocked synthesizable peripherals via an on-chip synchronous peripheral bus. As such it is capable of forming the core of a wide range of system-on-chip applications, bringing asynchronous design into commercial use in a flexible and easy-to-use configuration. Its performance and area are comparable with clocked equivalents, and its low-power and electromagnetic emission characteristics give it unique capabilities in appropriate applications.

Register locking in an asynchronous microprocessor

A high-performance register bank is a central component of a RISC processor. A novel register bank design has been developed, as an integral part of a self-timed implementation of a commercial RISC microprocessor, to address the problem of register interlocking in an asynchronous micropipelined execution unit. The problem in an asynchronous design is to maintain coherent register operation while allowing concurrent read and write accesses with arbitrary timing. The solution presented here includes a novel arbiter-free locking mechanism which enables efficient read operations in the presence of multiple pending write operations.<<ETX>>

The design and evaluation of an asynchronous microprocessor

AMULET1 is a fully asynchronous implementation of the ARM microprocessor which was designed at Manchester University between 1991 and 1993. First silicon arrived in April 1994 and was found to be functional, demonstrating that asynchronous design of complex circuits is feasible with present day CAD tools. This paper presents the motivation for the work, some of the design choices which were made, the problems which were encountered during the development of the design and the characteristics of the device itself. The future potential for asynchronous circuits is also discussed.<<ETX>>

Simulating asynchronous architectures on transputer networks

Recently, there has been a resurgence of interest in asynchronous design techniques due to the potential of asynchronous logic for higher performance, power efficiency and immunity from clock related timing problems. Occam, a CSP based parallel language provides for the rapid development of asynchronous architectural simulation models which may then be executed on a transputer network to achieve high performance. The paper discusses issues related to the design and execution of such models.

Occam: an asynchronous hardware description language?

Recently, there has been a resurgence of interest in asynchronous hardware due to the potential of asynchronous logic for higher performance, power efficiency and immunity from clock-related timing problems. This activity has revealed the current lack of suitable languages and notations for the description of asynchronous hardware systems anti has fueled an intense research effort in this area. Communicating sequential processes (CSP) in particular have attracted the interest of many researchers as a potential means for the modelling of asynchronous designs. Contributing to this effort, this paper examines whether Occam, a CSP-based language, may provide a solution to this endeavour.

Event-Driven Configuration of a Neural Network CMP System over a Homogeneous Interconnect Fabric

Configuring a million-core parallel system at boot time is a difficult process when the system has neither specialised hardware support for the configuration process nor a preconfigured default state that puts it in operating condition. SpiNNaker is a parallel Chip Multiprocessor (CMP) system for neural network (NN) simulation. Where most large CMP systems feature a sideband network to complete the boot process, SpiNNaker has a single homogeneous network interconnect for both application inter-processor communications and system control functions such as boot load and run-time user-system interaction. This network improves fault tolerance and makes it easier to support dynamic run-time reconfiguration, however, it requires a boot process that is transaction-level compatible with the application’s communications model. Since SpiNNaker uses event-driven asynchronous communications throughout, theloader operates with purely local control: there is no global synchronisation, state information, or transition sequence. A novel two-stage “unfolding” boot-up process efficiently configures the SpiNNaker hardware and loads the application using a high-speed flood-fill technique with support for run-time re-configuration. SystemC simulation of a multi-CMP SpiNNaker system indicates an error-free CMP configuration time of 1.3ms, while a high-level simulation of a full-scale system (64K CMPs) indicates a mean application-loading time of ∼20ms (for a 100KB application), which is virtually independent of the sizeof the system. We verified the CMP configuration process with hardware-level Verilog simulation.

Timing verification for asynchronous design

This paper describes a technique for verifying timing conditions inherent in self-timed VLSI designs that make use of the micropipeline design strategy. By checking bundling constraints during simulations, design faults may be detected, whilst timing information extracted during the processing may be used to identify modules requiring optimisation. These analyses may be built around existing simulators.