Paul Day

Four-phase micropipeline latch control circuits

Standard micropipelines use simple two-phase control circuits. The latches employed on AMULET1 are level sensitive, so two- to four-phase converters are required in each latch controller. To avoid this overhead an investigation has been carried out into four-phase micropipeline control circuits; this has thrown up several design issues relating to cost, performance and safety, and forms a useful illustration of asynchronous design techniques.

Investigation into micropipeline latch design styles

An asynchronous implementation of the ARM microprocessor has been designed and fabricated based on Sutherlands Micropipeline approach. Reviews of this work have shown that considerable performance improvement may be possible in a number of key design areas. This paper assesses the effects of different design styles on the micropipeline latch structures used. The original design has latch structures based on pass-transistor transparent latches. An evaluation of the use of single-phase transparent latch structures is given plus the application of 2-phase and 4-phase control techniques. >

AMULET1: an asynchronous ARM microprocessor

An asynchronous implementation of the ARM microprocessor has been developed using an approach based on Sutherlands Micropipelines. The design allows considerable internal asynchronous concurrency. This paper presents the rationale for the work, the organization of the chip, and the characteristics of the prototype silicon. The design displays unusual properties such as nondeterministic (but bounded) prefetch depth beyond a branch instruction, a data dependent throughput, and employs a novel register locking mechanism. This work demonstrates the feasibility of building complex asynchronous systems and gives an indication of the costs and benefits of the Micropipeline approach.

AMULET2e: an asynchronous embedded controller

AMULET2e is an embedded system chip incorporating a 32-bit ARM-compatible asynchronous processor core, a 4-Kb pipelined cache, a flexible memory interface with dynamic bus sizing, and assorted programmable control functions. Many on-chip performance-enhancing and power-saving features are switchable, enabling detailed experimental analysis of their effectiveness. AMULET2e silicon demonstrates competitive performance and power efficiency, ease of system design, and it includes innovative features that exploit its asynchronous operation to advantage in applications that require low standby power and/or freedom from the electromagnetic interference generated by system clocks.

AMULET1: a micropipelined ARM

A fully asynchronous implementation of the ARM microprocessor has been developed in order to investigate the potential of asynchronous logic for low-power applications. The work demonstrates the feasibility of complex asynchronous design and shows that the cost and performance characteristics are similar to clocked designs. AMULET1 is the first attempt at applying asynchronous techniques to a design of this complexity and as such there is much room for improvement. The authors introduce the design approach and organisation of the chip; they then cover the lessons learned from the first design and point towards future strategies for its enhancement and the likely benefits which will accrue from mature asynchronous technology.<<ETX>>

Register locking in an asynchronous microprocessor

A high-performance register bank is a central component of a RISC processor. A novel register bank design has been developed, as an integral part of a self-timed implementation of a commercial RISC microprocessor, to address the problem of register interlocking in an asynchronous micropipelined execution unit. The problem in an asynchronous design is to maintain coherent register operation while allowing concurrent read and write accesses with arbitrary timing. The solution presented here includes a novel arbiter-free locking mechanism which enables efficient read operations in the presence of multiple pending write operations.<<ETX>>

The design and evaluation of an asynchronous microprocessor

AMULET1 is a fully asynchronous implementation of the ARM microprocessor which was designed at Manchester University between 1991 and 1993. First silicon arrived in April 1994 and was found to be functional, demonstrating that asynchronous design of complex circuits is feasible with present day CAD tools. This paper presents the motivation for the work, some of the design choices which were made, the problems which were encountered during the development of the design and the characteristics of the device itself. The future potential for asynchronous circuits is also discussed.<<ETX>>

A low-power, low noise, configurable self-timed DSP

This paper describes a commercial implementation of a self-timed DSP. The self-timed design is fully compatible with a synchronous implementation allowing comparisons of both design styles to be made. The self-timed implementation has shown many benefits over its synchronous counterpart especially with regards power consumption and noise emissions. It also demonstrates the commercial viability of self-timed designs in power and noise sensitive applications. This paper also introduces the concept of a highly configurable Application Specific Integrated Architecture (ASIA/sup TM/).