Stephen B. Furber

Four-phase micropipeline latch control circuits

Standard micropipelines use simple two-phase control circuits. The latches employed on AMULET1 are level sensitive, so two- to four-phase converters are required in each latch controller. To avoid this overhead an investigation has been carried out into four-phase micropipeline control circuits; this has thrown up several design issues relating to cost, performance and safety, and forms a useful illustration of asynchronous design techniques.

AMULET1: an asynchronous ARM microprocessor

An asynchronous implementation of the ARM microprocessor has been developed using an approach based on Sutherlands Micropipelines. The design allows considerable internal asynchronous concurrency. This paper presents the rationale for the work, the organization of the chip, and the characteristics of the prototype silicon. The design displays unusual properties such as nondeterministic (but bounded) prefetch depth beyond a branch instruction, a data dependent throughput, and employs a novel register locking mechanism. This work demonstrates the feasibility of building complex asynchronous systems and gives an indication of the costs and benefits of the Micropipeline approach.

AMULET2e: an asynchronous embedded controller

AMULET2e is an embedded system chip incorporating a 32-bit ARM-compatible asynchronous processor core, a 4-Kb pipelined cache, a flexible memory interface with dynamic bus sizing, and assorted programmable control functions. Many on-chip performance-enhancing and power-saving features are switchable, enabling detailed experimental analysis of their effectiveness. AMULET2e silicon demonstrates competitive performance and power efficiency, ease of system design, and it includes innovative features that exploit its asynchronous operation to advantage in applications that require low standby power and/or freedom from the electromagnetic interference generated by system clocks.

AMULET1: a micropipelined ARM

A fully asynchronous implementation of the ARM microprocessor has been developed in order to investigate the potential of asynchronous logic for low-power applications. The work demonstrates the feasibility of complex asynchronous design and shows that the cost and performance characteristics are similar to clocked designs. AMULET1 is the first attempt at applying asynchronous techniques to a design of this complexity and as such there is much room for improvement. The authors introduce the design approach and organisation of the chip; they then cover the lessons learned from the first design and point towards future strategies for its enhancement and the likely benefits which will accrue from mature asynchronous technology.<<ETX>>

An investigation into the security of self-timed circuits

Self-timed logic may have advantages for security-sensitive applications. The absence of a clock, as a reliable timing reference, makes conventional power analysis attacks more difficult. However, the variability of the timing of self-timed circuits is a weakness that could be exploited by alternative attack techniques. This paper introduces a methodology for the differential power analysis of self-timed circuits which does not rely upon a clock signal. This methodology is used to investigate the security of a self-timed, ARM-compatible processor designed specifically to explore the benefits of self-timed design in secure applications. Timing analysis is also applied to the same design. The results from the analyses are presented and confirm that self-timed logic with dual-rail encoding and secure storage significantly improves resistance to non-invasive attacks.

Built-in self-testing of micropipelines

An asynchronous ARM6 microprocessor (AMULET1), designed at the University of Manchester using a two-phase signalling protocol, and the latest release of the AMULET2e embedded controller implemented using four-phase signalling, have proved the practical feasibility of the micropipeline design approach. A built-in self-test (BIST) micropipeline design based on an asynchronous BILBO register is presented in this paper. All the stage registers of the micropipeline are implemented using the proposed asynchronous BILBO register which can operate in four modes: normal operation, shift, linear feedback shift register (LFSR) and signature analyser mode. The test procedure described in this paper provides for the detection of all single stuck-at faults in the micropipeline. It is shown that delay faults in the combinational logic blocks of the BIST micropipeline can be tested by using BLBO registers of a doubled size.

Scan testing of micropipelines

The micropipeline approach to designing asynchronous VLSI circuits has successfully been used in the AMULET1 microprocessor. A method to design and test micropipelines is presented in this paper. The test strategy is based on the scan test technique. It allows the separate testing of all the data processing blocks by scanning the test patterns in and shifting the responses out of the stage registers. The proposed test approach provides for the detection of all single stuck-at and delay faults in the micropipeline. Tests for the combinational processing logic and state holding elements can be derived using standard test generation techniques.

Scan testing of asynchronous sequential circuits

A method to design and test asynchronous sequential circuits (ASCs) based on the micropipeline design style is presented in this paper. According to the proposed scan test approach the combinational block is tested separately by scanning the test vectors in and shifting the responses out of the state registers. This provides for the detection of all single stuck-at and delay faults in the ASC under test. The complexity of the test procedure of such a testable ASC is reduced to that of the combinational circuit. Tests for the combinational circuit and state holding elements can be derived using standard test generation techniques.

The return of asynchronous logic

There is now compelling evidence that asynchronous design is, indeed, feasible on CMOS VLSI, since several complex asynchronous chips have been built and shown to work. The work at Philips amply demonstrates power savings (at least within a particular application domain) and their elegant Tangpam synthesis tools support the concurrency claim. However, much more needs to be done to validate all these claims. Perhaps more convincing is the increasing industrial interest. Among the established players, Philips and Sun have invested considerable internal resource in asynchronous technology, and recently Intel has shown active interest. Whenever a significant technology change is foreseen, start-up companies form to exploit the inertia of the multinationals, and asynchronous logic can now claim at least two such new companies.

An asynchronous victim cache

Memory bandwidth is a limiting factor with many modem microprocessors and it is usual to include a cache to reduce the amount of memory traffic. Of the two commonly used cache write-policies, the copy-back approach is better than the write-through approach in this respect. The performance of both approaches can be further aided by the inclusion of a small buffer in the path of outgoing writes to the main memory, especially if this buffer is capable of forwarding its contents back into the main cache if they are needed again before they are emptied from the buffer This is what is known as a victim cache. For an asynchronous microprocessor it is logical that the cache system should be asynchronous as well; since a large degree of the flexibility of an asynchronous microprocessor would be lost if it were to use a standard synchronous memory interface. However implementing a forwarding mechanism in an asynchronous system is more difficult because the data to be forwarded is flowing in a manner unsynchronised to the process which requires it. This paper presents an architecture for a victim cache to resolve forwarding in a totally asynchronous environment. The resultant structure forms a key part of an asynchronous copy-back cache system for the Amulet3, a third generation asynchronous implementation of the ARM processor.