John W. Evans

Quality Conformance and Qualification of Microelectronic Packages and Interconnects

Three--Dimensional Stacked Dies. Cofired Ceramic Substrates. Organic Laminated Substrates and Chip--on--Board. High--Density Interconnects and Deposited Dielectrics. Wire and Wirebonds. Tape Automated Bonds. Flip--Chip Bonds. Device and Substrate Attachment. Cases. Leads. Lead Seals. Lid Seals. Material and Product Evaluation Methods. Rework Methods. Bibliography. Index.

Packaging factors affecting the fatigue life of power transistor die bonds

This paper presents an overview of die bond fatigue and a study of packaging and assembly factors and their influence on power transistor cyclic life. Power transistors with soft solder die bonds will fail by catastrophic failure, under cyclic conditions, as fatigue cracks develop and propagate through the die bond. Susceptibility to catastrophic failure increases over the life of the device, as crack growth through the die bond destroys the capability of the device to transfer heat. Power cycling tests followed by failure analysis show that die bond thickness has the most significant effect on catastrophic failure, followed by die bond thickness variation. Analysis shows, that for a given device, the die bond is not uniform and that the nonuniformity or die tilt (ratio of average to minimum thickness) influences device life by affecting strain concentration and crack growth. Oxygen content in the package, also influences device life to a lesser extent, as indicated by a statistical analysis of residual gas analysis results compared to cyclic life. This can be explained by crack closure effects during the development of die bond fatigue cracks. These findings further the understanding of die bond physics of failure and underscore the importance of optimizing die bond thickness in design and limiting variations and oxygen content in hermetic metal packages, during device manufacturing and assembly.

Simulation of fatigue distributions for ball grid arrays by the Monte Carlo method

Abstract Any approach to qualification of advanced technologies during product development must include an assessment of variation expected in product life over the life cycle. However, testing product design options in development, to approach an optimal design is costly and time consuming. Hence, simulation of product life distributions for virtual qualification can be a valuable tool to evaluate and qualify design options. This paper presents a physics of failure-based approach to virtual qualification of advanced area array assemblies against solder fatigue failure. The approach applies Monte Carlo simulation to evaluate solder joint fatigue life distributions, given material property variations and manufacturing capabilities. Preliminary results using the simple Engelmaier model as the basis of simulations are presented. Simulation results are compared to data accumulated from two test environments and two ball grid array product types. The results reveal some of the limitations of the Engelmaier model as a basis for simulation. They also show the potential of this approach to virtual qualification for design and manufacturing capability assessment in development.

Thermomechanical failures in microelectronic interconnects

Abstract Thermomechanical fatigue failures are an important class of failures in microelectronic interconnect structures. Thermomechanical stresses arise from differences in the coefficients of thermal expansion of the various materials comprising a microelectronics circuit. Polymer dielectrics and adhesives have larger coefficients of expansion than metal conductors. Dielectrics and adhesives may also exhibit large anisotropy in the coefficient of expansion, producing significant thermomechanical stresses in vias or other metal interconnect structures. During ambient thermal cycling or operational power dissipation, cyclic stresses are induced, which cause fatigue failures. The basic elements of thermomechanical fatigue behavior of microelectronic interconnect structures, such as lines and vias, are presented in this paper. In addition, a case study illustrating many of the concepts is presented for a complex 3-D interconnect.

THE EFFECT OF MANUFACTURING AND DESIGN PROCESS VARIABILITIES ON THE FATIGUE LIFE OF THE HIGH DENSITY INTERCONNECT VIAS

Via fatigue failure has been identified4 as a potential failure mechanism in high density interconnects. This failure mechanism is directly influenced by the stress-strain level at the potential points of failure in the structure and the ductility of the via material. This paper looks at the effect of some manufacturing and design process variables on the fatigue life of the vias. The key variables are the trace or conductor thickness (metallization thickness), the layer or layers of the dielectric around the trace and in the via, the via geometry, wall slope, the ductility coefficient of the conductor material and the strain concentration factor. The metallization thickness is found to have the most dramatic effect on the fatigue life of the via compared to the other design variables. Good via ductility and strain concentration factors improve the fatigue life drastically.

Effects of humidity and temperature cycling on 3-D packaging

Three dimensional electronics packaging technologies are emerging for many electronics system applications. Characterizing failure mechanisms, was the focus of this research. Accelerated testing and observing samples at various stages of the testing, with an Environmental Scanning Electron Microscope, were the primary methods used. Interfacial debonding of polyimides and fatigue cracking in bus structures were observed in humidity cycling and thermal cycling. These failures were the result of differential expansion of polyimide adhesives and dielectrics and interfacial degradation by moisture absorption.

Risk analysis for CGA and advanced electronics packaging

This paper first presents packaging technology trends and accelerated reliability testing and life projection methods that are being practiced by industry. Specifically, it presents industry status on key advanced electronic packages, factors affecting accelerated solder joint reliability of area array packages and approaches for characterizations of assemblies under accelerated thermal loading. Examples on projecting cycles-to-failure (CTF) from one accelerated thermal cycle condition to another for column grid arrays (CGAs) also presented. It was shown, even for thermal cycling, the limitation of projection using mildly accelerated thermal CTFs to a more severe accelerated thermal CTFs, both for CGA assembled with eutectic tin-lead solder and ball grid array (BGA) Pb-free assemblies. Examples also given for projection life of complex spacecraft using accelerated testing and analysis; thereby, reducing risk. Quantitative assessments necessarily involve the mathematics of probability and statistics. In addition, accelerated tests need to be designed which consider the desired risk posture and schedule for particular project. Such assessments relieve risks without imposing additional costs and constraints that are not value added for a particular mission.

Development of acceleration factors for reliability testing of mechanical equipment

Accelerated life tests allow for reduction of test time to demonstrate targeted life of a component for a given level of reliability. This is accomplished by increasing loads on the component or by compressing the time scale in relation to the service environment. The acceleration factor provides a quantitative estimate of the relationship between the test condition and the field condition for this purpose. This paper provides a detailed process, for developing acceleration factor models for reliability testing of mechanical components. Several examples are given for various types of mechanical components undergoing wear-out processes.

Accelerated Testing and Data Analysis

In Chapter 10, we examined the basic elements of testing and test design issues. Then, in Chapter 11, we turned our attention to multiple factors, multiple test conditions and test design for model development using designed experiments. We will now address accelerated testing and the statistical analysis of data from accelerated tests