Jon V. Osborn

Application of hardness-by-design methodology to radiation-tolerant ASIC technologies

Radiation-hard ASIC design is enabled by the trend in commercial microelectronics toward increased radiation hardness, demonstrated here with new radiation results on a 0.25-/spl mu/m commercial process utilizing shallow trench isolation. A design comparison is made between creating ASICs targeting a traditional rad-hard foundry, which may be more than two generations behind commercial foundries, applying hardness-by-design methodology at a commercial foundry, and directly targeting a commercial foundry using commercial design practices.

SEU test techniques for 256 K static RAMs and comparisons of upsets by heavy ions and protons

Test procedures needed to observe the single-event phenomena for various 256 K CMOS/NMOS static RAMs are described. The tests were conducted with both protons and heavy ions, yielding correlated comparisons of results. Most of the single-event vulnerability data were obtained using EDI EDH8832C, IDT IDT71256, OMNI-WAVE OW62256, and RCA XCDM62256 32 K*8 static RAMs. Among the four device types only OW62256s were resistant to single-event latchup. Estimates of the single-event-upset (SEU) rate in space show that OW62256s are the least susceptible devices. The test and reduction methods took into consideration multiple upsets caused by a single ion, the effect of read/write access time, and scaling related to feature size. The scaling study was made possible by comparing the SEU test results of an additional four types of radiation-hardened IDT static RAMs. >

Total dose hardness of three commercial CMOS microelectronics foundries

We have measured the effects of total ionizing dose (TID) on CMOS FETs, ring oscillators and field-oxide transistor test structures fabricated at three different commercial foundries with four different processes. The foundries spanned a range of integration levels and included Hewlett-Packard (HP) 0.5 /spl mu/m and 0.8 /spl mu/m processes, an Orbit 1.2 /spl mu/m process, and an AMI 1.6 /spl mu/m process. We found that the highest tolerance to TID was for the HP 0.5 /spl mu/m process, where the shift in NMOS threshold voltage was less than 40 mV at 300 krad. An examination of the dependence of the threshold voltage shift on gate oxide thickness indicated that oxides of the different commercial processes were of similar quality, and that the improvement in the total dose tolerance of the HP 0.5 /spl mu/m technology is associated with the scaling of the gate oxide. Measurements on field-oxide transistors from the HP 0.5 /spl mu/m process were shown not to invert for signal voltages at 300 krad, maintaining the integrity of the LOCOS isolation. The impact of these results is, discussed in terms of the potential insertion of commercial microelectronics into space systems.

Radiation Hardness of

Semiconducting TiO2 displays non-volatile multi-state, hysteretic behavior in its I-V characteristics that can be exploited as a memory material in a memristive device. We exposed memristive TiO2 devices in the on and off resistance states to 45 Mrad(Si) of ~1-MeV gamma radiation and 23 Mrad(Si) of 941-MeV Bi-ions under zero bias conditions and none of the devices were degraded. These results suggest that TiO2 memristive devices are good candidates for radiation hard electronics for aerospace.

{\rm TiO}_{2}

The use of annular MOSFET design, which has demonstrated total-dose radiation immunity in CMOS circuits, can improve the hot-carrier reliability of CMOS circuits by reducing the drain electric field compared to conventionally designed MOSFETs. A theoretical analysis of the annular n-MOSFET in saturation verifies the reduction of the drain electric field in properly designed MOSFETs. Hot-carrier data for an enclosed 0.25-/spl mu/m n-MOSFET demonstrate an improvement in hot-carrier lifetime by more than 3x compared to a conventional device in the same technology.

Memristive Junctions

TiO2 memristor devices may be a promising candidate for radiation hardened next-generation memories. They have been shown to be tolerant to both gamma radiation and alpha particles. In this work, we expand on the radiation studies previously done and measure the response of a large number of TiO2 memristor test devices to both neutrons and protons. We also use simulations to estimate the amount of damage done for each type and level of radiation and correlate the number of displacements to the experimentally measured current-voltage characteristics of the devices. We show that the TiO2 thin films are tolerant to high fluences of both neutrons and protons.

Reliability enhancement in high-performance MOSFETs by annular transistor design

The insertion of microelectromechanical systems (MEMS) components into aerospace systems requires advanced testing to characterize performance in a space environment. Here, we report a novel stroboscopic interferometer test system that measures nanometer-scale displacements of moving MEMS devices. By combining video imagery and phase-shift interferometry with an environmental chamber, rapid visualization of the dynamic device motion under the actual operational conditions can be achieved. The utility of this system is further enhanced by integrating the interferometer onto the chamber window, allowing for robust interferometric testing in a noisy environment without requiring a floating optical table. To demonstrate these unique capabilities, we present the time-resolved images of an electrostatically actuated MEMS cantilevered beam showing the first-order to sixth-order plate modes under vacuum.

Displacement Damage in TiO

This paper describes the fabrication and characterization of a micromachined, micro hot plate (MHP) sensor substrate for chemical sensor applications. The MHPs were fabricated using a silicon-processing foundry followed by a novel combination of laser and chemical etching of individual die. An IR microscope was used for thermal imaging of the MHP and shows that the device is very efficient (11.5°C/mW) and has a fast response time (30 ms). The performance of the MHP is compared to thermal measurements on a commercial sensor substrate; the MHP consumes almost 30 times less power. The MHPs also have very good performance as compared to other similar micromachined devices described in the literature. From efficiency measurements of devices in air and in vacuum, heat loss by conduction in air is determined to be ∼30% larger than conduction through the membrane. The measured thermal efficiency in vacuum and in air is consistent with expectations based on simple analytical models, the thermal conductivities of the membrane and air, and the MHP geometry. Data are presented on the high-temperature, thermal failure mode of the devices using scanning electron microscopy and energy dispersive X-ray analysis. At temperatures close to the Si-Au eutectic point, we find that the gold metallization fails due to interaction with underlying polysilicon layer.

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We have developed a radiation-hardened, highly linear, wideband, low-noise amplifier (LNA) with programmable gain to serve as the front-end of a plasma-wave instrument for satellite-based electric-field measurements of very low frequency (VLF) phenomena in the Van Allen radiation belts. Fabricated in a commercial 0.25-mum silicon-germanium BiCMOS process, this ASIC leverages radiation-hardness-by-design techniques at the topological, implementation, and layout levels to maintain 75-dB spurious-free dynamic range (SFDR) over nearly four decades of frequency, from 100 Hz to 1 MHz, for both proton and gamma-ray total ionizing dose (TID) exposures up to 1000 krad(Si). Single-event effect (SEE) testing via pulsed laser confirms negligible latchup sensitivity and suppression of single-event transients (SETs) at the output for beam energy LET equivalents in excess of 100MeV-cm2 /mg in even the most sensitive regions of the die

Memristor Devices

Memristor devices have been identified as potential replacements for a variety of memory applications and may also be suitable for space applications. In this work, we present a review of radiation testing on TiO2-based memristor devices. The experimental results from three previous studies are reviewed and coupled here with modeling to gain a more complete understanding of the energy deposition and resulting effects on the electrical performance of the device. In addition, we discuss the implications of having a nanometer scaled thin film device and how that affects the energy deposition from the various radiation sources.