Jonas E. Huber

Optimum number of cascaded cells for high-power medium-voltage multilevel converters

When power electronic systems are connected to the medium-voltage grid, often multilevel topologies consisting of a number of cascaded converter cells are considered. For a given grid voltage level, either few cells featuring semiconductors with high blocking voltage capability or many cells using low-voltage semiconductors can be employed. This paper proposes efficiency/power density (η-ρ) Pareto analysis to comprehensively identify the optimum number of cascaded cells. Recent advances in silicon carbide (SiC) semiconductor technology point towards devices with blocking voltages exceeding 15kV. The switching characteristics that hypothetical SiC devices would have to provide in order to realize a simple single-stage full-bridge converter competitive to a multilevel solution are derived and found to be impracticably fast. Furthermore, it is shown that reliability concerns arising with increasing number of cascaded cells can be mitigated by means of redundancy.

Volume/weight/cost comparison of a 1MVA 10 kV/400 V solid-state against a conventional low-frequency distribution transformer

Solid-State Transformers (SSTs) are an emergent topic in the context of the Smart Grid paradigm, where SSTs could replace conventional passive transformers to add flexibility and controllability, such as power routing capabilities or reactive power compensation, to the grid. This paper presents a comparison of a 1000 kVA three-phase, low-frequency distribution transformer (LFT) and an equally rated SST, with respect to volume, weight, losses, and material costs, where the corresponding data of the SST is partly based on a full-scale prototype design. It is found that the SSTs costs are at least five times and its losses about three times higher, its weight similar but its volume reduced to less than 80%. In addition, an AC/DC application is also considered, where the comparison turns out in favor of the SST-based concept, since its losses are only about half compared to the LFT-based system, and the volume and the weight are reduced to about one third, whereas the material costs advantage of the LFT is much less pronounced.

Solid-State Transformers: On the Origins and Evolution of Key Concepts

During the past two decades, solid-state transformers (SSTs) have evolved quickly and have been considered for replacing conventional low-frequency (LF) transformers in applications such as traction, where weight and volume savings and substantial efficiency improvements can be achieved, or in smart grids because of their controllability. As shown in this article, all main modern SST topologies realize the common key characteristics of these transformers-medium-frequency (MF) isolation stage, connection to medium voltage (MV), and controllability-by employing combinations of a very few key concepts, which have been described or patented as early as the 1960s. But still, key research challenges concerning protection, isolation, and reliability remain.

Analysis and design of fixed voltage transfer ratio DC/DC converter cells for phase-modular solid-state transformers

Many Solid-State Transformer (SST) concepts employ cascaded AC/DC converter cells to handle the comparatively high medium-voltage (MV) grid voltages, resulting in a phase-modular structure. Accordingly, each cell - formed by an AC/DC input stage and an isolated DC/DC output stage - processes a power fluctuating with twice the grid frequency. The series resonant converter (SRC) operated in the half-cycle discontinuous-conduction-mode (HC-DCM) is a highly attractive choice for the isolated DC/DC converter because of its high efficiency. However, this converter does not offer any control possibilities; instead, it couples the two DC voltages through certain dynamics with fixed voltage transfer ratio. This leads to a propagation of the input side power fluctuations through the SRC to the common LV bus, which has certain consequences on the converter design. The paper therefore re-derives a dynamic model of the SRCs terminal behavior in a generic way, which also covers the case of comparatively small DC link capacitors. The experimentally verified dynamic model is then used to discuss and optimize the choice of the input and output side capacitances of the DC/DC converter cell with respect to the placement of the converters system level resonances, such as to obtain minimum volume and losses. Finally, aspects related to the design of a scaled demonstrator system featuring similar dynamic behavior as the full-scale system are addressed and first measurement results are presented.

η-ρ Pareto optimization of bidirectional half-cycle discontinuous-conduction-mode series-resonant DC/DC converter with fixed voltage transfer ratio

In solid-state-transformer technology, the isolation and power transfer between low voltage and medium voltage side is performed by a high power DC/DC converter. This DC/DC converter provides a defined ratio between input and output voltages, whereby, in order to reduce switching losses, zero-current-switching modulation schemes are often mandatory. The series-resonant-converter operated in half-cycle discontinuous-conduction-mode possesses all the aforementioned features, thus making it highly attractive for solid-state-transformer applications. For this reason, a comprehensive analytical model of the converters static and dynamic behavior is provided in this paper. In addition, a method to model the switching losses under ZCS conditions, which is based on the behavior of the stored charge in the semiconductors, is presented. This enables an efficiency/power density (η-ρ) Pareto optimization of the aforementioned converter system.

Operating behavior and design of the half-cycle discontinuous-conduction-mode series-resonant-converter with small DC link capacitors

The series-resonant-converter operated in half-cycle discontinuous-conduction-mode is a realization option for bidirectional isolated DC/DC converter modules, which are key components of modern solid state transformer (SST) concepts, among other applications. In SSTs the DC/DC converters are interfacing the input and output inverter stages via DC links. For reasons of costs as well as possible application-specific restrictions on weight and volume it is beneficial to use as small DC link capacitors as possible. However, when the resonant capacitance is higher than about 10% of the DC link capacitances, the deviation of the resonant current waveform from the sinusoidal shape becomes significant and the half-cycle duration is altered from values calculated using common approaches. Here, a comprehensive discussion of this case is given and design guidelines for the choice of the resonant capacitor are derived. The importance of the effect is illustrated by applying these to a complete design example.

New modulation and control scheme for phase-modular isolated matrix-type three-phase AC/DC converter

A phase-modular isolated three-phase AC/DC converter topology and its modulation and control scheme is proposed. The topology, denominated as IMY-Rectifier, is based on a star connection of single-phase mains frequency to high frequency AC/AC matrix converters at the input, feeding high-frequency isolation transformers. The transformer secondary windings are connected in series to the input of a diode rectifier with LC output filter. The converter provides a controlled output voltage and sinusoidal input currents in phase with the mains voltages. A description of the converter, its operating principle and an analytical calculation of the component stresses is presented.

Design and Experimental Testing of a Resonant DC–DC Converter for Solid-State Transformers

In the solid-state transformer (SST) concept, the key task of voltage adaptation and isolation is performed by a high-power dc–dc converter, which is operated in the medium-frequency range, hence enabling a reduction in size and weight of the converters reactive components. This dc–dc converter presents the main challenge in the implementation of the SST concept, given its operation at medium frequency together with the direct connection to medium voltage. This combination demands the utilization of dc–dc converter topologies that are able to operate in the soft-switching mode, whereby, given that typically insulated-gate bipolar transistor switches are used as power devices, zero-current switching modulation schemes become highly attractive and often mandatory in order to achieve the targeted efficiency goals. This paper describes in detail the analysis and design of a 166-kW/20-kHz dc–dc converter of the series-resonant type, which results to be particularly interesting for high-power applications, given its tight input-to-output transfer characteristics and its capability to ensure soft-switching transitions of all semiconductor devices. The main focus of this paper is to describe in detail the practical implementation of the aforementioned resonant dc–dc converter, where its main components, i.e., the medium- and low-voltage-side power bridges and the medium-frequency transformer, are described independently. The assembled prototype is presented together with the implemented testing strategy and the final experimental results.

Comparative evaluation of isolated front end and isolated back end multi-cell SSTs

Solid-state transformers (SSTs) are power electronic interfaces between medium voltage (MV) and low voltage (LV) systems that provide galvanic isolation by means of medium frequency (MF) transformers, making them suitable for MVAC to LVDC conversion in environments where weight and volume constraints apply. This paper discusses an isolated front end (IFE) SST concept that allows to reduce the complexity and physical size of the MV side converter assemblies compared to the well-known isolated back end (IBE) SST topologies. The IFE approach performs the entire grid current and output voltage control on the LV side using standard non-isolated |AC|-DC boost converter stages. A generic comparison of the IFE and the IBE concepts reveals that the lower complexity of the IFE, e. g., a lower total MV blocking voltage requirement (number of cascaded cells), comes along with higher device RMS currents and hence slightly higher chip area requirements. On the other hand, a case study considering a 25kW, 6.6 kV AC to 400V DC SST shows advantages of the IFE in part-load operation due to lower switching and transformer core losses. This makes the IFE approach interesting for applications where MF isolation instead of low frequency isolation is required because of space and weight constraints (e. g., traction, subsea or aircraft environments), and where low system complexity is desirable.

Litz wire losses: Effects of twisting imperfections

High-Frequency (HF) litz wires are extensively used for the windings of Medium-Frequency (MF) magnetic components in order to reduce the impact of eddy current losses that originate from skin and proximity effects. Literature documents different methods to calculate eddy current losses in HF litz wires, however, most of the computation methods rely on perfect twisting of the strands, which is often not present in practice. This paper analyzes the implications of imperfect twisting on the current distribution among the different strands of HF litz wires and the corresponding losses by means of a fast 2.5D PEEC (Partial Element Equivalent Circuit) method. The effects of different types of twisting imperfections (at the bundle-, sub-bundle-, or strand-level) are examined. It is found that imperfect twisting can lead to increased losses (more than 100 %). However, perfect twisting of the strands, which is difficult to achieve, is often not required, i.e. suboptimal twisting is sufficient. Analytical expressions are given for distinguishing between critical and uncritical imperfections. The experimental results, conducted with a 7.5kHz/65kW transformer, reveal a reduction of the error on the predicted losses from 52 % (ideal HF litz wire model) to 8 % (presented model) and, thus, confirm the accuracy improvement achieved with the proposed approach.