Daniel J. Deleganes

Low-voltage swing logic circuits for a Pentium/spl reg/ 4 processor integer core

The Pentium/spl reg/ 4 processor architecture uses a 2/spl times/ frequency core clock to implement low latency integer operations. Low-voltage-swing (LVS) logic circuits implemented in 90-nm technology meet the frequency demands of a third-generation integer-core design.

Low-voltage-swing logic circuits for a 7GHz x86 integer core

Pentium/spl reg/4 processor architecture uses a 2x core clock to implement low latency integer operations. Low-voltage-swing logic circuits in 90nm technology meet the frequency demands of a 3rd generation integer core, with operation demonstrated for frequencies in excess of 7GHz.

Low voltage swing logic circuits for a Pentium 4 processor integer core

The Pentium/spl reg/ 4 processor architecture uses a 2/spl times/ frequency core clock to implement low latency integer operations. Low-voltage-swing (LVS) logic circuits implemented in 90-nm technology meet the frequency demands of a third-generation integer-core design.

A 150 MHz 0.6 μm BiCMOS superscalar microprocessor

An implementation of the Pentium microprocessor architecture in 0.6 /spl mu/m BiCMOS technology is described. Power dissipation is reduced and performance is enhanced over the previous generation. Processor features, implementation technology, and circuit techniques are discussed. An internal clock rate of 150 MHz is achieved at 3.7 V and -55/spl deg/C. >

A mixed signal rotator/shifter for 8GHz Intel/spl reg/ Pentium/spl reg/ 4 integer core

A novel mixed signal 32-bit rotator/shifter circuit design enabling ultra-short latency Intel/spl reg/ Netburst/spl trade/ rotate and shift instructions is described. Compared to previous generation Intel/spl reg/ Pentium/spl reg/ 4 processor designs, this implementation cuts Rotate/Shift latency and throughput by 75% while adding significant frequency headroom. The circuit manufactured on Intels 90nm process confirms a significant boost in integer performance.

A 150 MHz 0.6 /spl mu/m BiCMOS superscalar microprocessor

An implementation of the Pentium microprocessor architecture in 0.6 /spl mu/m BiCMOS technology is described. Power dissipation is reduced and performance is enhanced over the previous generation. Processor features, implementation technology, and circuit techniques are discussed. An internal clock rate of 150 MHz is achieved at 3.7 V and -55/spl deg/C. >

150 MHz 0.6 μm BiCMOS superscalar microprocessor

An implementation of the Pentium microprocessor architecture in 0.6 /spl mu/m BiCMOS technology is described. Power dissipation is reduced and performance is enhanced over the previous generation. Processor features, implementation technology, and circuit techniques are discussed. An internal clock rate of 150 MHz is achieved at 3.7 V and -55/spl deg/C. >