Jong-Hak Won

Data output buffer control circuit of a synchronous semiconductor memory device

Merged memory and logic (MML) integrated circuits including memory test controlling circuits and methods

Memory device having reduced layout area

Scalable hierarchical I/O line structure for a semiconductor memory device

Memory device having minimized power consumption and data read and write method of the same

Layout structure of bit line sense amplifier of semiconductor memory device

Semiconductor memory device and signal line arrangement method thereof

Area-efficient data line layouts to suppress the degradation of electrical characteristics

Data line layouts

LAYOUT METHOD OF SEMICONDUCTOR DEVICE WITH JUNCTION DIODE FOR PREVENTING DAMAGE DUE TO PLASMA CHARGE