Hak-soo Yu

A SRAM Core Architecture with Adaptive Cell Bias Scheme

This paper describes an adaptive cell bias scheme that is proposed to achieve high performance and stability for a low power, high speed, and high density SRAM core with less process variation. The proposed scheme is featured with constrained-successive cell bias optimization method that determines the optimal cell bias condition sequentially to meet both the speed and stability target of a given SRAM core. The architecture with adaptive cell bias scheme is applied to a 144Mb double stacked S3 SRAM and leads to 49% reduction in SRAM core performance parameter variations with 8% area overhead. The power reduction is 21%