Jong-Kai Lin

Direct correlation between microstructure and mechanical tensile properties in Pb-free solders and eutectic SnPb solder for flip chip technology

The relationship between the microstructure and the mechanical tensile properties of lead-free solders and eutectic SnPb solders is presented for flip chip scale interconnects. Eutectic Sn–37Pb and Sn–0.7Cu solder (in wt %) exhibited a ductile fracture after tensile testing. Eutectic Sn–3.5Ag solder (in wt %) had greater strength and exhibited a brittle fracture at the interface. The different fracture behavior of the lead-free solders was attributed to the grain size and configuration of the intermetallics. Minor additions of alloying elements to the high Sn lead-free solder dramatically affected the microstructure and mechanical properties.

Interfacial reaction of eutectic AuSi solder with Si (100) and Si (111) surfaces

The dissolution behavior of Si (100) and (111) dies by eutectic AuSi solder was investigated. On the Si (100) surface, the dissolution primarily occurred by the formation of craters resulting in a rough surface. The dissolution of the Si (111) resulted in a relatively smooth surface. The morphology of the Si (100) surface during a AuSi soldering reaction exhibited more time-dependent behavior and the etching craters on a Si (100) surface grew larger with time whereas Si (111) did not significantly change. This difference was ascribed to the surface energy differences between Si (111) and (100) surfaces that resulted in the two- and three-dimensional dissolution behaviors, respectively. This difference plays an important role in the formation of voids during the AuSi die bonding. The etching craters on Si (100) act as a AuSi solder sink and the regions surrounded by etch pits tend to become voids. For Si (111), flat surfaces were observed in the voided regions. Cross section analysis showed that no solder ...

Conductive polymer bump interconnects

Conductive polymer bonded flip chip interconnect systems can provide an attractive alternative flip chip technology in terms of cost and manufacturability. This work examines the feasibility of application of such a technology. A mathematical model for stencil printing of conductive adhesive paste is developed to demonstrate some of the factors affecting the print quality. Designed experiments is used to optimize bump dimensional uniformity. The electrical performance of conductive polymer flip chip interconnects is evaluated through both GaAs and Si devices. The microwave insertion loss (S/sub 21/) of a coplanar waveguide test vehicle showed a loss rate of 0.031 dB/GHz for non-underfilled flip chip assembly and 0.065 dB/GHz for those with underfill encapsulation. These S/sub 21/ data are almost identical to a device with same test structure and a Au ball bumped flip chip assembly. Additional test using a CT-2 antenna switch GaAs device flip chip bonded on a FR4 board showed an identical performance (up to 2 GHz frequency) to the same assembly using Au-Sn eutectic bumps. Reliability of conductive polymer bumps was evaluated using Si die flip chip bonded on FR4 substrates. Results showed no failures on temperature cycle, humidity, vibration, and mechanical shock tests. There were 8.6% failures on HAST and 6% failures on thermal shock tests on test conditions stated in the text.

Thermal fatigue properties of lead-free solders on Cu and NiP under bump metallurgies

Three Pb-free solders, SnCu0.7, SnAg3.8Cu0.7 and SnAg3.5 were evaluated on both electroless NiP and electroplated Cu under bump metallurgies (UBM) for flip chip applications. Eutectic SnPb37 solder was also evaluated as a baseline comparison with the Pb-free solders. Test dice with a size of 12.6/spl times/7.5 mm/sup 2/ were direct flip chip attached to test boards with variety of solder alloy/UBM combinations. In order to accelerate solder bump fatigue, no underfill encapsulation was used on the assembled parts. Due to high CTE mismatch between the Si and PCB and low stand-off height of the flip chip assembly, conditions of 0 to 100/spl deg/C and -40 to 125/spl deg/C air-to-air thermal cycling were performed to maximize cycles to failure and to distinguish the fatigue life among the solder alloys/UBMs. The results showed that the SnCu0.7 solder, on both electroless NiP and electroplated Cu UBMs, had the longest thermal fatigue life among all the solder/UBM interconnect structures evaluated. The SnAg3.8Cu0.7 on electroplated Cu had a thermal fatigue life comparable to eutectic SnPb37 while SnAg3.5 on electroless NiP had the worst thermal fatigue life. The failure mechanism varied among the Pb-free solder/UBM combinations. The SnCu on both NiP and Cu UBMs had cohesive failure inside the solder bump due to extensive creep in this alloy during thermal cycling. Both SnAg3.5 on electroless NiP UBM and SnAg3.8Cu0.7 on electroplated Cu UBM showed fatigue cracks initiated and propagated through intermetallics and along the intermetallic/solder interfaces, resulting in a shorter thermal fatigue life. Based on these results, the SnCu0.7 solder alloy appears to be the best choice for Pb-free flip chip interconnect.

Lead-free flip chip interconnect reliability for DCA and FC-PBGA packages

A variety of Pb-free solders and under bump metallurgies (Cu, Ni, NiP) were investigated for flip chip packaging applications. The result shows that Sn-0.7Cu exhibits the most desirable mechanical properties (shear, tensile, aging, etc.) during deformation under a variety of stress conditions and has the most favorable failure mechanism under both mechanical and thermomechanical stress testing regardless of UBM type. The eutectic Sn-0.7Cu failed through bulk solder while the eutectic Sn-37Pb, Sn-3.5Ag and Sn-3.8Ag-0.7Cu failed at the solder and UBM interface, involving their respective intermetallic compounds. Cu UBM is more favorable for better reliability than NiP UBM from both interface IMC morphology and electromigration points of view. The current carrying capability for all alloys had no failures when stressed up to 2,338 hours at 2.6/spl times/10/sup 4/ A/cm/sup 2/ and 170/spl deg/C. However, when stressed at 5.1/spl times/10/sup 4/ A/cm/sup 2/, there is a significant migration of Pb toward the anode, creating a multiple layered Pb-rich and Sn-rich microstructure. An observation of excessive Ni migration away from the NiP UBM towards the anode after only 30 hours of current stressing at 5.1/spl times/10/sup 4/ A/cm/sup 2/ and 150/spl deg/C raised the reliability concern for solders with NiP UBM, especially for high power applications. The Sn-0.7Cu/Cu UBM and Sn0.7Cu/Ni UBM exhibit greater than 5,300 cycles of thermal fatigue characteristic life under -55/spl deg/C 1+150/spl deg/C and -40/spl deg/C /+125/spl deg/C air-to-air thermal cycling conditions, respectively.

Reliability evaluations of chip interconnect in lead-free solder systems

Chip interconnect (solder to silicon) reliability is one of the critical elements in the qualification of flip-chip bumping technology. Since the interconnect materials, structures and processes vary in different bumping technologies, the strength and reliability must be evaluated for each design. As lead-free solders are used in the system, the intermetallics associated with the lead-free solders and the UBM (under bump metallurgy) has also influence on the interconnect reliability. In addition, the stress that an interconnect experiences during thermal cycling depends on the properties of the solder alloy used in the interconnect. Different solder alloys require different interconnect strengths to achieve good reliability in thermal cycling. This paper reports on a study of interconnect reliability by comparing the interconnect strength and the working stress in the interconnect during qualification and application. A simple stress model was developed to determine the interconnect stress during thermal cycling. A testing methodology was established for determining the interconnect strength. In this report, the reliability of several interconnect structures in several lead-free solder systems, including Sn/Ag, Sn/Ag/Cu and Sn/Cu solders and the Ni-Au and TiW-Cu UBMs were studied.

Squeegee bump technology

An innovative solder bumping technology, termed squeegee bumping, has been developed at Motorolas Interconnect Systems Laboratory that uses baked photoresist as a mask for solder printing to deposit fine pitch solder bumps on wafers. This process provides much better alignment accuracy and is capable of bumping finer pitch devices than stencil printing technology. Solder paste printing uses a screen printer similar to that used for stencil printing. Greater versatility of solder materials can be obtained through solder paste than the electroplating. Cost modeling shows that the squeegee bump technology has a significant cost benefit over controlled collapse chip connection (C4) technology. This is because the C4 process has very low efficiency in labor and materials usage. Statistical process control data show an average bump height of 118 /spl plusmn/ 3.5 /spl mu/m, and a maximum-to-minimum bump height range of 17 /spl mu/m over a 150 mm-diameter wafer and have been produced repeatedly on test wafers with 210 /spl mu/m peripheral pitch. A 109.6 /spl plusmn/ 1.3 /spl mu/m bump height on orthogonal array with 250 /spl mu/m pitch has been successfully demonstrated with greater than 90% die yield. Bump reliability has been studied using both multiple reflows and extended thermal/humidity storage procedures. No degradation of shear strength was observed after up to 10 /spl times/ reflows and 1008 h of a thermal/humidity stress environment. Bump reliability was also evaluated by assembling squeegee bumped dice on a plastic chip scale package (CSP). Liquid-to-liquid thermal shock cycling at a temperature range of -55/spl deg/C to +125/spl deg/C had a characteristic life of 2764 cycles with a 1st failure at 1050 cycles. No failures were observed after 432 h of autoclave stress at 121/spl deg/C, 100% RH, 15 psig test condition.

Characterization of lead-free solders and under bump metallurgies for flip-chip package

A variety of Pb-free solders and under bump metallurgies (UBMs) was investigated for flip chip packaging applications. The result shows that the Sn-0.7Cu eutectic alloy has the best fatigue life and it possess the most desirable failure mechanism in both thermal and isothermal mechanical tests regardless of UBM type. Although the electroless Ni-P UBM has a much slower reaction rate with solders than the Cu UBM, room temperature mechanical fatigue is worse than on the Cu UBM when coupled with either Sn-3.8Ag-0.7Cu or Sn-3.5Ag solder. The Sn-37Pb solder consumes less Cu UBM than all other Pb-free solders during reflow. However, Sn-37Pb consumes more Cu after solid state annealing. Studies on aging, tensile, and shear mechanical properties show that the Sn-0.7Cu alloy is the most favorable Pb-free solder for flip chip applications.

Interfacial reaction of eutectic AuSi solder with Si

The dissolution behavior of Si (100) and (111) dice by eutectic AuSi solder was investigated. On the Si (100) surface, the dissolution primarily occurred by the formation of craters resulting in a rough surface. The dissolution of the Si ( I 11) resulted in a relatively smooth surface. The morphology of the Si (100) surface during AuSi soldering reaction exhibited more time-dependent behavior and the etching craters on Si (100) surface grew larger with time whereas Si ( I 11) did not significantly change. This difference was ascribed to the surface energy differences between Si (111) and (100) surfaces that resulted in the 2and 3dimensional dissolution behaviors, respectively. This difference plays an important role in the formation of voids during AuSi die attach. The etching craters on Si (100) act as a AuSi solder sink and the regions surrounded by etch-pits tend to become voids. For Si ( I l l ) , flat surfaces were observed in the voided regions. Cross-section analysis showed that no solder reaction had occurred in voided region of Si (1 1 I ) surface. This suggests the possibility of the formation of a thin inert layer in a potentially voided region prior to assembly. In order to achieve void-free die attach, different parameters must be adjusted to Si (100) and Si (1 11) surfaces with the AuSi alloy.