Darrel R. Frear

Spalling of Cu3Sn intermetallics in high-lead 95Pb5Sn solder bumps on Cu under bump metallization during solid-state annealing

We report the spalling of Cu3Sn intermetallics in high-lead 95Pb5Sn solder bumps on Cu under bump metallization (UBM) during solid state annealing. Upon reflow, the Cu3Sn intermetallics formed on Cu UBM. However, after solid state annealing at 170 °C, the Cu3Sn intermetallics spalled off from Cu UBM and the Pb phase filled the gap between the Cu3Sn intermetallics and Cu UBM. This is primarily explained by the loss of chemical adhesion between the Cu3Sn intermetallics and Cu UBM due to no additional chemical reaction. Thermodynamic principles are used to interpret the spalling phenomenon and the analysis showed that the interfacial free energy without spalling is greater than that with spalling after solid-state annealing. Spalling of the Cu3Sn intermetallics initiated at an open interface such as the edge of Cu UBM and finally extended to the flat interface at a slower rate.

Failure Morphology After Drop Impact Test of Ball Grid Array (BGA) Package With Lead-Free Sn–3.8Ag–0.7Cu and Eutectic SnPb Solders

High strain-rate drop impact tests were performed on ball grid array (BGA) packages with solder compositions of (in wt%) Sn-3.8Ag-0.7Cu (SnAgCu) and eutectic Sn-37Pb (SnPb). Solder balls were joined to the metallizations of plated Ni on the device side and plated Cu on the board side. The BGA packages were tested at 1500 g within 0.5 ms, resulting in an imposed bending strain of 0.2-0.3%. Both SnAgCu and SnPb joints failed at the interface at the device side but the detailed failure morphology differed significantly. The crack location for the eutectic SnPb was primarily through the solder and seldom extended through an entire bump. The SnPb joints also exhibited bulk solder deformation. The SnAgCu joints showed extremely brittle behavior with an interfacial failure at the (Ni,Cu)3Sn4 intermetallics/Ni under bump metallization (UBM) interface. The strain rate sensitivity of bulk solder defines the drop test performance and the eutectic SnPb solder showed better drop impact performance due to a less strain rate sensitivity

Motorola MEMS switch technology for high frequency applications

Motorola Semiconductor Products Sector (SPS) has made significant progress in developing an integrated MEMS switch network for use in next-generation portable wireless systems. This MEMS switch technology has significantly better RF characteristics than conventional PIN diodes or FET switches and consumes less power. The RF MEMS switch exhibits insertion loss under 0.3 dB, isolation greater than 50 dB, and operating power under 200 /spl mu/W. The RF MEMS switch chip is integrated with a high voltage charge pump plus control logic chips into a single package that provides a network system to accommodate low voltage requirements in portable wireless applications.

System-in-a-package integration of SAW RF Rx filter stacked on a transceiver chip

Demands for mobile phones with smaller form factor and lower cost have driven enhanced integration of electronics components. However, surface acoustic wave (SAW) filters must be fabricated on piezoelectric substrates, and so they are difficult to monolithically integrate on semiconductor chips. This paper reports on a compact wafer-scale packaged SAW filter stacked over a transceiver chip in a quad flat-pack no-lead (QFN) package. An integrated passive device (IPD) provided redistribution and matching between the SAW filter output and the transceiver input. Both extended global system for mobile communications (EGSM) and DCS filters were evaluated. Results demonstrated that conventional packaging techniques could be used to successfully assemble stacked SAW on transceiver modules without damage. SAW compact models based on the coupling of modes model were developed to facilitate system design. Electromagnetic simulations of coupling between SAW filters and inductors integrated on the transceiver suggested that design care is needed to avoid interactions, especially if an IPD is not used as a spacer. With appropriate design, stacked SAW filter on transceiver offers viable module integration.

Electromigration behavior of lead-free solder flip chip bumps on NiP/Cu metallization

The electromigration behavior of Sn–2.5Ag and Sn–0.7Cu (in wt %) flip chip solder joints on electroless NiP/Cu metallization at a current density of 1.3×104 A/cm2 was studied. For Sn-2.5 Ag solder, electromigration at 115 °C for 250 h showed a selective dissolution of Ni from the electroless NiP layer forming crystallized Ni3P. At 140 °C, the damage to the NiP layer was accelerated and instability of the NiP/Cu interface was observed. For eutectic Sn–0.7Cu solder, the electromigration behavior at a higher temperature was evaluated. At 180 °C, the NiP/Cu under bump metallurgy (UBM) started to show damage after 50 h. At 200 °C, the entire NiP/Cu layer was damaged, and P in the NiP layer moved to the edge of the anode much faster than the other species forming CuP2 intermetallics. NiP/Cu UBM experiences selective dissolution of Ni at lower temperatures, and the damage of the entire UBM occurred abruptly at the higher temperature.

Emerging reliability challenges in electronic packaging

The trend for microelectronic devices has historically been, and will continue to be, towards smaller feature size, faster speeds, more complexity, higher power and lower cost. The motivating force behind these advances has traditionally been microprocessors. With the tremendous growth of wireless telecommunication, RF applications are beginning to drive many areas of microelectronics traditionally led by the development of the microprocessor. An increasingly dominant factor in RF microelectronics is electronic packaging and the reliability of the package and the materials that comprise the package and, in particular, the solder interconnects. The need for Pb-free assembly and the application to hand-held electronics has challenged the reliability of electronic packages. This paper discusses packaging reliability of solder interconnects for hand-held wireless and RF applications and describe the tests used to evaluate reliability. The specific reliability issues discussed will be thermomechanical stress (fatigue), solder joint electromigration (DC and RF) and high speed impact stresses (drop test performance).

Tensile fracture behaviors of solid-state-annealed eutectic SnPb and lead-free solder flip chip bumps

The tensile fracture behavior for solid-state-annealed eutectic SnPb and lead-free solder flip chip bumps was examined. The annealing temperatures were in the range of 125-170 °C for 500 h. Prior to solid state annealing,the eutectic Sn-37Pb (SnPb) and Sn-0.7Cu (SnCu) solders showed fracture through the bulk solder. Brittle interfacial fracture occurred in the Sn-3.5Ag (SnAg) solder. After solid-state annealing, the fracture behavior changed dramatically. For eutectic SnPb solder, the fracture modes gradually changed from cohesive solder failure to interfacial fracture with increasing annealing temperature. The fracture mode of the SnCu solder showed greater change than the SnPb and SnCu solders. After annealing at 125 °C, the SnAg solder had a ductile taffy pull fracture, but an increase in temperature resulted in brittle interfacial fracture again. The SnCu solder maintained the same ductile taffy pull mode up to 170 °C annealing, independent of the under bump metallization (UBM) type. Microstructure analysis showed that the interfacial fracture of the SnPb and SnAg solder bumps was ascribed to Pb-rich layer formation and Ag embrittlement at the interface, respectively. The bulk solder fracture of SnAg annealed at 125 °C appeared to be a transient phenomenon due to the abrupt breakdown of the hard lamella structure. The eutectic SnCu solder bumps had no significant change in the interfacial structure, except for interfacial intermetallic growth.

Electromigration behavior of flip-chip solder bumps subjected to RF stressing

A test system was built to evaluate RF electromigration characteristics of solder interconnections. The test system measured DC resistance and RF insertion loss and testing was done with high frequency RF signals superimposed on 0 A, 0.25 A or 0.5 A of DC current at elevated temperatures. The test vehicle consisted of daisy chain test Si die with Sn0.7Cu flip chip bumps on 11 mum of plated Cu/Cu/TiW UBM and GaAs die with Sn2.5Ag flip chip bumps on 2 mum plated Ni/Ti UBM. RF stressing resulted in brittle intermetallic structures on the surface of the solder bumps, which is not seen with pure DC stressing. Furthermore, the RF energy created damage through electromagnetic induction current on neighboring unstressed bumps. The superimposition of a 0.5 A DC current on the RF signal accelerated the bump damage rate. In this paper a description of the daisy chain test vehicle, factors considered in RF electromigration testing, variation of DC resistance and RF insertion loss with time, failure analysis using cross-sections and SEM will be used to explain the effect of RF stressing on solder bump behavior.

Interfacial reaction of eutectic AuSi solder with Si

The dissolution behavior of Si (100) and (111) dice by eutectic AuSi solder was investigated. On the Si (100) surface, the dissolution primarily occurred by the formation of craters resulting in a rough surface. The dissolution of the Si ( I 11) resulted in a relatively smooth surface. The morphology of the Si (100) surface during AuSi soldering reaction exhibited more time-dependent behavior and the etching craters on Si (100) surface grew larger with time whereas Si ( I 11) did not significantly change. This difference was ascribed to the surface energy differences between Si (111) and (100) surfaces that resulted in the 2and 3dimensional dissolution behaviors, respectively. This difference plays an important role in the formation of voids during AuSi die attach. The etching craters on Si (100) act as a AuSi solder sink and the regions surrounded by etch-pits tend to become voids. For Si ( I l l ) , flat surfaces were observed in the voided regions. Cross-section analysis showed that no solder reaction had occurred in voided region of Si (1 1 I ) surface. This suggests the possibility of the formation of a thin inert layer in a potentially voided region prior to assembly. In order to achieve void-free die attach, different parameters must be adjusted to Si (100) and Si (1 11) surfaces with the AuSi alloy.