Jongchol Kim

Comprehensive extensibility of 20nm low power/high performance technology platform featuring scalable high-k/metal gate planar transistors with reduced design corner

Extensibility of the high-k/metal gate (HK/MG) planar devices beyond 20nm node with high performance, low power consumption, less layout dependence and suppressed local variability were comprehensively studied among gate first (GF) and gate-last (GL) schemes for the first time. We demonstrated the N-/PFET drive current (Idsat) of 1.45/1.3 mA/μm with the off-leakage current (Ioff) of 100 nA/μm for the Vdd of 0.9V by scaling down the gate width (Wg) of GL-HK/MG devices to 60nm. Key layout dependence of the PFET with embedded SiGe source/drain (eSiGe) was improved by eSiGe interface engineering and scaling down the Wg with keeping the multiple threshold voltage (Vt) and improving the body-bias effect (BE). Moreover, we demonstrated reduction in the capacitance by conventional method even for such a scaled planar device. Finally, we achieved the sufficiently low Vt mismatch, which is required to reduce the design corner, by eSiGe interface engineering and reduction of interface states in the gate stack (Dit).

Performance evaluation of FinFETs: From multisubband BTE to DD calibration

This paper presents a hierarchical approach to link the advanced multisubband Boltzmann transport equation (MSBTE) solver to the conventional drift-diffusion (DD) model for performance evaluation of non-planar transistors in logic technology development. An automated, physics-based procedure to extract the DD model parameter set from the MSBTE simulation is described. An update on the surface roughness scattering model valid for finite barriers is also shown. As an application, the MSBTE to DD calibration is performed for a silicon nanowire transistor. The calibrated parameter set is applied to a dual channel nanowire transistor, and the effects of the source/drain series and contact resistances are studied.

Layout-induced stress effects on the performance and variation of FinFETs

Recently, LLEs(Local Layout Effects) and their impact on performance due to STI stressor and eSiGe S/D have been reported in FinFETs[1]. However, the impacts of gate and contact stress are rarely demonstrated. In this paper, we extended the LLE factors to the gate and contact and analyzed their impact on the electrical parameters of mobility, IdSat and VtSat via TCAD simulation study. This work shows that 5(20)% of n(p)FET performance enhancement and only 1(2)% of IdSat variation can be obtained through optimal stress components aligned with LLE factors.

Comprehensive Simulation Study of Direct Source-to-Drain Tunneling in Ultra-Scaled Si, Ge, and III-V DG-FETs

As the scaling of transistors approaches the 7-/5-nm technology nodes, direct source-to-drain tunneling (SDT) is becoming increasingly important with the shrinking gate lengths. In this paper, we present a comprehensive simulation study on the effects of SDT in ultrascaled FETs with various channel materials (Si, Ge, SiGe, InGaAs, and so on), surface/channel orientation configurations, gate lengths, body thicknesses, doping concentrations, stress levels, and temperatures. The nonequilibrium Green’s function formalism with the atomistic tight-binding basis is used to accurately model both the quantum-mechanical tunneling and the bandstructure effects. To quantify the strength of SDT, we propose a current ratio (

Multi-domain compact modeling for GeSbTe-based memory and selector devices and simulation for large-scale 3-D cross-point memory arrays

\beta

Band-to-Band Tunneling in SiGe: Influence of Alloy Scattering

), which essentially illustrates the difference between a full quantum transport model and a semiclassical model for calculating the FET OFF-current. The results clearly show that SDT strongly depends on orientations and stress levels in the FET channel, and for materials with a small transport effective-mass (e.g., Ge and InAs), SDT dominates the total OFF-current, making it difficult to achieve a low OFF-current target at a scaled gate length. In addition, it is found that the temperature dependence of the FET OFF-current decreases with the strength of SDT, which may have an implication on the technology definition and device targeting for the 7-/5-nm nodes.

Impact of BTBT, stress and interface charge on optimum Ge in SiGe pMOS for low power applications

A novel compact model is developed by coupling comprehensive physical equations from electrical, thermal and phase-transition domains in order to capture their correlations that exist in GeSeTe (GST) device physics. Several non-ideal effects during GST-based memory cell operations have been studied with particular focus on cell Read/Write margins and reliability issues. Finally, large-scale 3-D cross-point memory array circuits have been simulated with developed physics-based models to further explore the design constraints.

On the efficient methods to solve multi-subband BTE in 1D gas systems: Decoupling approximations versus the accurate approach

An improved band-to-band tunneling (BTBT) model for SiGe random alloy is presented. The model takes into account the coherent transition through the direct band gap as well as the phonon and alloy scattering induced transitions to the indirect conduction band valleys. The complex valence and conduction band structures obtained from the 6-band

Atomistic simulation of band-to-band tunneling in SiGe: Influence of alloy scattering

{k}\cdot {p}

Nanoscale-nMOSFET junction design: Quantum transport approach

and from the multi-valley effective mass models are combined to compute the non-parabolic imaginary dispersions for the direct and indirect BTBT transitions, which agree well with the full band calculations. The present model is validated against the atomistic quantum simulation based on the empirical tight binding method. Simulation results show that the alloy scattering plays an important role in the indirect BTBT of SiGe alloy and should not be neglected.