Uihui Kwon

Novel stress-memorization-technology (SMT) for high electron mobility enhancement of gate last high-k/metal gate devices

High-k/metal gate (HKMG) compatible high performance Source/Drain (S/D) stress-memorization-technology (SMT) is presented. Channel stress generated by SMT can be simulated by using mask-edge dislocation model, which is consistent with the measured actual channel stress. Extremely deep pre-amorphization-implant (PAI) for SMT creates multiple mask-edge dislocations under S/D region, which enhances short-channel mobility by 40∼60%. Finally, more than 10% short channel drive current gain is achieved with additional S/D extension optimization.

A practical Si nanowire technology with nanowire-on-insulator structure for beyond 10nm logic technologies

This paper reports the design and fabrication of a practical Si nanowire (NW) transistor for beyond 10 nm logic devices application. The dependency of the DC and AC performances of Si NW MOSFETs on NW diameter (DNW) and gate oxide thickness has been investigated. A Si NW device with the scaled DNW of 9 nm and thin equivalent oxide thickness (EOT) of 0.9 nm improved both on-current and electrostatic characteristics. Finally, a Nanowire-On-Insulator (NOI) structure has been proposed to enhance the AC performance of a multiple-stacked NWs structure, which improves DC performance but has the issue of high parasitic capacitance. As a result, the simulated AC performance of a triple-NOI structure was improved by around 20% compared to conventional triple NW structure.

A novel tensile Si (n) and compressive SiGe (p) dual-channel CMOS FinFET co-integration scheme for 5nm logic applications and beyond

A novel tensile Si (tSi) and compressive SiGe (cSiGe) dual-channel FinFET CMOS co-integration scheme, aimed at logic applications for the 5nm technology node and beyond, is demonstrated for the first time, showing electrical performance benefits and excellent co-integration feasibility. A Strain-Relaxed SiGe Buffer (SRB) layer is introduced as buried stressor and successfully transfers up to ∼1 GPa uniaxial tensile and compressive stress to the Si/SiGe n-/p-channels simultaneously. As the result, both tSi and cSiGe devices show a 40% and 10% electron and hole mobility gain over unstrained Si, respectively. Through a novel gate stack solution including a common interfacial layer (IL), HK, and single metal gate for both n- and pFET, secured process margin for 5nm gate length, low interface trap density (Dit) for SiGe channel and threshold voltage (Vt) target for both the Si and SiGe device are successfully demonstrated. Lastly, reliability investigation shows that tSi and cSiGe, employing the newly developed common gate stack scheme, possess superior reliability characteristics compared with those of equivalent Si devices.

In 0.53 Ga 0.47 As-Based nMOSFET Design for Low Standby Power Applications

III-V n-channel MOSFETs based on InxGa1-xAs are evaluated for low-power (LP) technology at a sub-10-nm technology node. Aggressive design rules are followed, while industry-relevant FinFET architecture is selected. We show, for the first time, quantum confinement-related leakage and performance tradeoff done self-consistently in performance evaluation using an in-house developed semiclassical tool. In this paper, we focus on In0.53Ga0.47As as the channel material, as it has been investigated heavily in the literature. Furthermore, it has a bulk bandgap EG similar to that of Ge, another highly studied complementary p-FET channel material. Higher In-content results in lower EG and hence larger band-to-band tunneling (BTBT) current, resulting in more stringent design requirements for LP applications. A comparison is done with the state-of-the-art tensile-Si (t-Si) technology, with roughly 2-GPa stress, under similar constraints LG, design rules). Thus, we show that while for 0.75 V operation, In0.53Ga0.47 As performance is limited by the BTBT and fails to outperform t-Si, it starts to perform better than t-Si below 0.7 V. VDD scaling further results in an increased performance gap between the two material systems.

Physical understanding of alloy scattering in SiGe channel for high-performance strained pFETs

For devices beyond the 14nm node, it is important to investigate performance boosters such as high mobility channels. Although pure Ge offers a higher hole mobility than Si, conventional problems like surface passivation and its integration with Si makes SiGe alloy with low Ge mole fraction a viable option. The significance of alloy scattering, however, has been widely debated [1-3], so the accurate modeling of alloy scattering in SiGe channel has become an important issue to predict the performance of future SiGe-based FETs. Usually, the calculation of alloy scattering mobility assumes an alloy scattering center in a simple analytical form with some fitting parameters, which is a good practical approach but has a limited predictability. In this paper, an atomistic tight-binding simulation is used to study alloy scattering in SiGe-based FETs, and to compare with experimental data. We conclude (i) although it is essentially impossible to avoid alloy scattering in SiGe material, (ii) high-mobility is indeed achieved in SiGe channel by combining lattice-mismatch stresses from Si virtual substrate with stresses from Source/Drain(SD) stressor.

Investigation of HCI reliability in interdigitated LDMOS

Novel time-dependent kinetic model for interface trap formation is developed resulting in consideration of hot electron/hole injection in Interdigitated LDMOS. Proposed kinetic model replaces Si-H equation with Nit equation. HCI degradation of Interdigitated LDMOS is classified into two mechanisms. First mechanism is attributed to decreased electron densities due to electron trapping in interdigitated active region. Second mechanism occurs in accumulation region around side STI due to hot hole injection. First mechanism leads to an increase in RON upon stress, whereas second mechanism decreases RON.

Layout-induced stress effects on the performance and variation of FinFETs

Recently, LLEs(Local Layout Effects) and their impact on performance due to STI stressor and eSiGe S/D have been reported in FinFETs[1]. However, the impacts of gate and contact stress are rarely demonstrated. In this paper, we extended the LLE factors to the gate and contact and analyzed their impact on the electrical parameters of mobility, IdSat and VtSat via TCAD simulation study. This work shows that 5(20)% of n(p)FET performance enhancement and only 1(2)% of IdSat variation can be obtained through optimal stress components aligned with LLE factors.

Impact of BTBT, stress and interface charge on optimum Ge in SiGe pMOS for low power applications

The feasibility of medium-high fraction SiGe based FinFET pMOS devices for a sub-10nm CMOS logic technology from a performance (IEFF @ fixed IOFF) standpoint is evaluated, considering three key device aspects - stress, band-to-band-tunneling (BTBT), and interface charge density (DIT). The analysis reveals that while for high Ge (>90%), performance is limited by BTBT, overall stress reduction beyond Ge 65% further limits performance. Including realistic (DIT) profile further shows that optimum Ge content is between 40%~50% for low power applications.

Charge-collection modeling for SER simulation in FinFETs

Soft-errors are one of the most important reliability issues in logic and memory circuits. Proper estimation of soft-error-rate (SER) is important for error mitigation and SER robust circuit design. This paper presents a physical charge collection model for accurate simulation/prediction of SER in FinFETs. The modeling is scalable and includes the effect of variation of FinFET process and layout parameters.

Efficient Monte Carlo simulation of ion implantation into 3D FinFET structure

Precise simulation of ion implantation is a crucial base point of Front End Process (FEP) TCAD. To meet both simulation accuracy target and achieve short turnaround time (TAT), an improved statistical enhancement method has been implemented in Monte Carlo ion implantation simulator. The approach used for statistical enhancement allowed lower lateral doping profile noise comparing to conventional method while using just a fraction of simulation time. The results led to significant TAT reduction for advanced Logic and Memory FEP simulations.