Kwi-Dong Kim

A 10b 205MS/s 1mm2 90nm CMOS Pipeline ADC for Flat-Panel Display Applications

A 10b 205MS/S 1mm2 ADC for flat-panel display applications is implemented in a 90nm CMOS process. The ADC with an LDO regulator achieves a 53dB PSRR for a 100MHz noise tone and a 55.2dB SNDR for a 30MHz 1Vpp single-ended input at 205MS/S. The core ADC power consumption is 40mW from a 1V non-regulated supply.

A 10-bit 400-MS/s 160-mW 0.13-/spl mu/m CMOS dual-channel pipeline ADC without channel mismatch calibration

This paper describes a 10-bit 400-MS/s dual-channel analog-to-digital converter (ADC) insensitive to offset, gain, and sampling-time mismatches between channels. An adaptive closed-loop sampling technique based on a multi-stage amplifier eliminates the channel offset effectively. Multi-stage amplifiers with high DC gain reduce the gain mismatch between channels and guarantee a large signal swing at low supply voltages. A single clock-edge sampling scheme for clock-skew reduction minimizes the sampling-time mismatch. The proposed prototype ADC in a 0.13-mum CMOS process occupies an active area of 4.2mm2, dissipates 160mW from 1.2 V and 400 MS/s, and shows a signal-to-noise-and-distortion ratio of 54.8 dB with a 29-MHz sinusoidal input at 400 MS/s without any channel-mismatch calibration technique. The measured maximum offset and gain mismatches are less than 0.1% and 0.2%, respectively

A 4.7mW 0.32mm2 10b 30MS/s Pipelined ADC Without a Front-End S/H in 90nm CMOS

A 4.7mW 10b 30MS/s pipelined ADC is implemented without a front-end S/H for low power consumption and small area. The prototype ADC, fabricated in a 90nm CMOS process, shows an SNDR of 58.4dB and an SFDR of 75.2dB with a 2MHz sinusoidal input sampled at 30MS/S. The 0.32 mm2 chip dissipates 4.7mW at a 1V supply and has a FOM of 0.23pJ/conversion-step.

A Dual-Channel Pipelined ADC With Sub-ADC Based on Flash–SAR Architecture

This brief presents a 10-bit dual-channel pipelined flash-successive approximation register (SAR) analog-to-digital converter (ADC) for high-speed applications. The proposed ADC consists of two channels for high operating speed, and each channel adopts a pipelined flash-SAR architecture for low power and a small area. The proposed flash-SAR ADC in the second stage is composed of a 1-bit flash ADC and a 6-bit SAR ADC considering the chip area, operation speed, and circuit complexity. The prototype ADC fabricated in a 45-nm CMOS process occupies 0.16 mm2. The differential and integral nonlinearities of the ADC are less than 0.36 and 0.67 LSB, respectively. The ADC shows a signal-to-noise-and-distortion ratio of 54.6 dB and a spurious-free dynamic range of 64.0 dB with a 78-MHz input at 230 MS/s with a 1.1-V supply. The maximum operating frequency of the ADC is 260 MS/s at a 1.2-V supply. The power consumptions of the ADC with 230 and 260 MS/s are 13.9 and 17.8 mW, respectively.

A 5-mW 0.26-mm2 10-bit 20-MS/s Pipelined CMOS ADC with Multi-Stage Amplifier Sharing Technique

This paper describes a 10-bit 20-Msample/s analog-to-digital converter (ADC) employing a multi-stage amplifier sharing scheme to reduce the power consumption and chip area at low supply voltages. The proposed scheme shares a multi-stage amplifier between a sample-and-hold amplifier and a first-stage multi-bit multiplying digital-to-analog converter by changing loop configurations of the amplifier. For further power and chip area reduction, the same resistor ladder is shared between the adjacent flash ADC blocks. The prototype ADC fabricated in a 0.13mum CMOS technology shows a signal-to-noise-and-distortion ratio of 56.0 dB and a spurious-free dynamic range of 68.7 dB with a 2-MHz sinusoidal input at 20 Msample/s. The ADC occupies 0.26 mm2 and dissipates 5 mW at a 1.2-V supply

A 105.5 dB, 0.49 mm 2 Audio ΣΔ modulator using chopper stabilization and fully randomized DWA

An audio S.modulator achieves 105.5 dB dynamic range over 20 kHz audio bandwidth. A chopper stabilization technique is used in both the first integrator and the reference buffer to prevent degradation of the dynamic range and the peak signal-to-noise-plus-distortion-ratio due to flicker noise. A fully randomized data weighted averaging is used as a dynamic element matching technique to suppress the generation of spurious tones with a negligible increase in the in-band noise compared to conventional data weighted averaging. The chip was fabricated in 0.13 mum CMOS technology (I/O devices) and occupies a small chip area of 0.49 mm2. The total power consumption is 9.9 mW from a 3.3 V supply.

Analysis of the electrical characteristics of novel ESD protection device with high holding voltage under various temperatures

The paper introduces a silicon controlled rectifier (SCR)-based device with high holding voltage for ESD power clamp. The holding voltage can be increased by extending a p+ cathode to the first n-well and adding second n-well wrapping around n+ cathode. The increase of the holding voltage above the supply voltage enables latch-up immune normal operation. The device is fabricated by 0.35um BCD (Bipolar-CMOS-DMOS) technology and investigated not only the electrical characteristics, but also temperature dependence of holding voltage/current in a wide temperature range from 300K to 500K. In the measurement result, the proposed device has holding voltage of 8V and second breakdown current of 80mA/um. At high temperature condition of above 400K, the holding voltage, holding current and second breakdown current of the proposed device rapidly decrease.

A 3.8-5.5-GHz Multi-Band CMOS Frequency Synthesizer for WPAN/WLAN Applications

In this paper, we present a 3.8-5.5 GHz multi-band CMOS frequency synthesizer for WLAN and UWB applications. In the multi-band frequency synthesizer, both new multi-mode prescaler and adaptive multi-band LC VCO are proposed. The proposed multi-mode prescaler produces six modes of divide-by-2/3, 4/5, 8/9, 16/17, 32/33, and 64/65. In the adaptive multi-band LC VCO, the gate width of cross-coupled MOS array is tuned to calibrate oscillation amplitude and alleviate 1/f flicker noise of MOS. The multi-band frequency synthesizer represents -121 dBc/Hz at 5 MHz offset from 5.24 GHz carrier. The multi-band frequency synthesizer consumes a total current of 26mA at 1.2 V, and is manufactured in 0.13-mum CMOS process technology

A 9.1-to-11.5-GHz Four-Band PLL for X-Band Satellite & Optical Communication Applications

In this paper, a 9.1 to 11.5 GHz four-band PLL is presented. In the proposed PLL, both an improved multi-modulus (MM) divider and an adaptive four-band LC VCO are depicted. The MM divider provides division ratios of 6 to 455 depending on the division mode of the six-mode prescaler. The LC VCO generates four bands of oscillation frequencies covering 9.1-11.6 GHz, including an adaptive cross-coupled MOS array. The cross-coupled MOS array was devised to reduce the area of the capacitor array and compensate for the oscillation power. The PLL achieves phase noises of -98 dBc/Hz from 11.4 GHz and -102 dBc/Hz from 9.61 GHz, at an offset of 980 kHz. The PLL consumes 32 mA at 1.2 V. It was fabricated using 130 nm CMOS process technology.

Material design schemes for single-transistor-type ferroelectric memory cells using Pt/(Bi, La)4Ti3O12/ONO/Si structures

We successfully fabricated metal-ferroelectric-insulator-semiconductor (MFIS) structures using Bi3.465La0.85Ti3O12 (BLT) ferroelectric thin films and SiO2/Si3N4/SiO2 (ONO) stacked buffer layers for single-transistor-type ferroelectric nonvolatile memory applications. The BLT films were deposited on the prepared Pt/Ti/SiO2/Si and ONO/Si substrates by a sol–gel spin-coating method. The dielectric constant and the leakage current density of the prepared ONO film were measured to be 5.6 and 1.0×10-9 A/cm2 at 3 MV/cm, respectively. We found that the material and electrical properties of the BLT films were effectively modulated by the crystallographic orientation control of the thin films, which were strongly affected by the first annealing process at relatively low temperature. While the fabricated MFIS capacitors using (117)-oriented BLT films showed a charge injection phenomenon in C–V properties at high operating voltage, c-axis-oriented BLT-loaded MFIS capacitors showed a memory window of 0.6 V even at a voltage sweep of ±8 V. We conclude from these results that the c-axis-oriented BLT films formed by the newly proposed fabrication method can be successfully applied to single-transistor-type ferroelectric memory cells.