Jongpil Jung

Hybrid cache architecture replacing SRAM cache with future memory technology

Recently, hybrid cache architecture has become illuminated. As heterogeneous memory dies are stacked, it improves the performance of microprocessor enhanced in terms of power consumption and processing speed. This paper analyzed the hybrid cache architecture using different programs and memory types. SRAM is fixed for L1 cache memory, whereas DRAM, MRAM, and PRAM are the candidates for L2 cache memory. Each memory structure has the area satisfying the least Average Memory Access Time (AMAT) under a given area condition. Architecture composed of SRAM and MRAM shows 16.9% reduction in average memory access time and 15.2% of power reduction compared with that composed of homogeneous SRAM. Structure of SRAM and DRAM represents 33.0% reduction in power consumption, and that of SRAM and PRAM shows a potential to reduce area and power consumption due to their high density.

A Dynamic Search Range Algorithm for Stabilized Reduction of Memory Traffic in Video Encoder

Embedded compression is commonly employed in a video codec to reduce the data traffic to/from off-chip frame memory. We proposed a method for maintaining the memory bandwidth requirement at a significantly reduced level through dynamic search range adjustment for the motion estimation based on the observed relationship between the compression ratio and the motion vector. This, together with the so-called “center moving” to adjust the newly incoming macroblocks, helped significantly lower the requirement of the memory bandwidth without a fluctuation. Experimental results have shown that the memory bandwidth requirement can be finally stabilized to 20% of that of the full search. The image quality degradation was merely 0.02 dB.

Design and management of 3D-stacked NUCA cache for chip multiprocessors

Power and delay induced from long on-chip interconnections are becoming major issues of chip multiprocessor design. Both network-on-chip (NoC) and three-dimensional integration are promising ways to mitigate the interconnection problem. In this paper, we explore the design of 3Dstacked non-uniform cache architecture (NUCA) with onchip network. In addition, this paper investigates the problem of partitioning shared L2 cache for concurrently executing multiple applications in order to improve the system performance in terms of instructions per cycle. The proposed design is evaluated in an integrated power, performance, and temperature simulator. Experimental results show that the proposed method enhances system performance by 23.3% and reduces energy consumption by 17.9% for 16-core processor system compared to conventional design.

Energy-Aware Operation of Black Box Surveillance Cameras under Event Uncertainty and Memory Constraint

In this paper, we propose an event-driven black box surveillance camera which reduces energy consumption by waking up the system only when an event is detected and dynamically adjusting the video encoding and the resultant image distortion according to the criticality of captured frames called significance level. To achieve this goal, we find an encoding bitrate minimizing the energy consumption of the camera while satisfying the limited memory space constraint and distortion requirement at each significance level by judiciously allocating bit-rate to each significance level. To do that, we considered the trade-off relations between the total energy consumption vs. encoding bit-rate according to the significance level. For further energy savings, we also proposed a low complexity solution which adjusts the energy-minimal encoding bit-rate based on the dynamically changing event behavior, i.e., timing and duration of events. Experimental results show that the proposed method yields up to 67.49% (49.19% on average) energy savings compared to the conventional bitrate allocation methods.

Maximizing throughput of temperature-constrained multi-core systems with 3D-stacked cache memory

Three-dimensional integration has the potential to increase integration density and to reduce communication latency of chip-multiprocessors (CMPs). However, high power density (i.e., power dissipation per unit volume) due to the high integration incurs temperature-related problems in reliability, power consumption, performance, and system cooling cost. In this paper, we propose a design-time solution for temperature-constrained multi-core systems with 3D stacked cache memory in order to maximize the instruction throughput. The proposed method combines power gating of memory banks in the 3D stacked cache memory, which adapts cache partitioning [7], and dynamic voltage and frequency scaling (DVFS) of each core in a temperature-aware manner. Experimental results show that the proposed method offers up to 32% (average 15%) performance improvement in terms of instructions per second (IPS) compared with an existing method which only performs cache partitioning without temperature consideration.

Latency-aware Utility-based NUCA Cache Partitioning in 3D-stacked multi-processor systems

Increasing number of processor cores on a chip is a driving force to move to three-dimensional integration. On the other hand, as the number of processor cores increases, non-uniform cache architecture (NUCA) receives growing attention. Reducing effective memory access time, including cache hit time and miss penalty, is crucial in such multi-processor systems. In this paper, we propose a Latency-aware Utility-based Cache Partitioning (LUCP) method which reduces memory access time in a 3D-stacked NUCA. To reduce the memory access time, the proposed method partitions shared NUCA cache for each processor core according to latency variation (depending on the physical distance from processor core to cache bank) and cache access characteristic of application programs. Experimental results show that the proposed method reduces memory access time by up to 32.6% with an average of 14.9% compared to conventional method [1].

Temperature-aware energy minimization of 3D-stacked L2 DRAM cache through DVFS

Three-dimensional (3D) memory stacking is one of the most promising applications in 3D integration to solve the limited memory bandwidth problem in 2D integrated circuits (ICs). However, the high power density, i.e., power dissipation per unit volume, due to the high integration density of 3D ICs may incur high operating temperature and, thus, causes low reliability as well as high power consumption. In this paper, we describes the effects of temperature, supply voltage, and L2 cache access rate on both power consumption and reliability of 3D-stacked L2 DRAM cache. Also, we propose a dynamic voltage and frequency scaling (DVFS) scheme for 3D-stacked L2 DRAM cache which can be adapted to either each cache bank or each group of cache banks while taking account of both error-rate and temperature-induced power consumption. Experimental results show that the proposed DVFS scheme achieved a reduction of energy consumption by up to 21.5% compared to a conventional scheme under a given error-rate constraint.

Runtime 3-D stacked cache data management for energy minimization of 3-D chip-multiprocessors

In a 3-D processor-memory system, multiple cache dies can be stacked onto multi-core die to reduce latency and power of the on-chip wires connecting the cores and the cache, which finally increases the power efficiency. However, there are two challenging issues. The first is the high power density (resulting from multiple die stacking) that incurs many temperature-related problems including temperature-dependent leakage power. The second is the processor-cache traffic congestions that occur at through-silicon vias (TSVs) shared by multiple stacked caches. In this paper, a runtime cache data mapping is proposed for 3-D stacked L2 caches to minimize the overall energy of 3-D chip multiprocessors (CMPs). The proposed method considers both temperature distribution and memory traffic of 3-D CMPs. Experimental result shows that the proposed method achieves up to 22.88% energy reduction compared to an existing solution which considers only the temperature distribution.

Static energy minimization of 3D stacked L2 cache with selective cache compression

Three-dimentional (3D) integration is one of the most promising approaches to increase cache bandwidth and to reduce the wire length and thereby, the delay and transmission power consumption. However, high power density in 3D IC due to dense integration incurs significant leakage current increment which leads to high static energy consumption. The leakage energy consumption of 3D-stacked cache memory is more serious than that of conventional cache memory in 2D ICs. In this paper, we propose a selective cache compression technique coupled with power gating to reduce the static energy consumption of 3D-stacked SRAM cache. Cache blocks are selected to be compressed in runtime according to the cache access pattern, so that the decompression overhead is reduced. The experimental results show that our method reduces energy consumption by up to 40% (22% on average) with negligible performance overhead compared with the conventional cache management policy.

Hybrid L2 NUCA Design and Management Considering Data Access Latency, Energy Efficiency, and Storage Lifetime

Nonvolatile magnetic RAM (MRAM) offers high cell density and low leakage power. This paper reports on using a 3-D integration technology based on through-silicon vias, to stack disparate memory technologies (e.g., SRAM and MRAM) together onto chip multiprocessors. In this paper, we explore the design of a 3-D stacked nonuniform hybrid SRAM/MRAM L2 cache architecture (NUCA) using the on-chip network to mitigate the interconnection problem. In addition, this paper investigates the problem of partitioning shared SRAM/MRAM hybrid L2 cache and placing cache data into the partitioned 3-D stacked hybrid NUCA for concurrently executing multiple applications in order to improve the system performance in terms of instructions per second while considering the heterogeneous characteristics in interconnection wire delay, memory cell density, memory access latency, and memory power consumption in a 3-D stacked hybrid SRAM/MRAM L2 cache. Experimental results show that the proposed runtime method with a 3-D stacked hybrid L2 cache improves performance by 61%, energy efficiency, i.e., energy-delay product by 53%, and storage lifetime by 15.6 times on average compared with the conventional SRAM-only L2 cache or MRAM-only L2 cache with the similar area.