Jaemoon Kim

A Lossless Embedded Compression Using Significant Bit Truncation for HD Video Coding

Increasing the image size of a video sequence aggravates the memory bandwidth problem of a video coding system. Despite many embedded compression (EC) algorithms proposed to overcome this problem, no lossless EC algorithm able to handle high-definition (HD) size video sequences has been proposed thus far. In this paper, a lossless EC algorithm for HD video sequences and related hardware architecture is proposed. The proposed algorithm consists of two steps. The first is a hierarchical prediction method based on pixel averaging and copying. The second step involves significant bit truncation (SBT) which encodes prediction errors in a group with the same number of bits so that the multiple prediction errors are decoded in a clock cycle. The theoretical lower bound of the compression ratio of the SBT coding was also derived. Experimental results have shown a 60% reduction of memory bandwidth on average. Hardware implementation results have shown that a throughput of 14.2 pixels/cycle can be achieved with 36 K gates, which is sufficient to handle HD-size video sequences in real time.

A lossless embedded compression algorithm for high definition video coding

With a rapid increase of image resolution in recent mobile video systems, the memory bandwidth and power consumption have surfaced as critical problems in video coding. Despite many embedded compression algorithms proposed to overcome these problems, no proper algorithms have yet been reported with high enough throughput and no quality loss. This paper first proposes a lossless embedded compression algorithm with high compression ratio along with the hardware architecture for high throughput. Experimental results show that the proposed algorithm achieves at least 60% data compression without quality loss and bitrate increment. Moreover, the latency of the proposed architecture is sufficient to meet the real-time requirement of high-definition video coding, i.e., 30 cycles/macroblock. The proposed algorithm can be implemented with about 28K gates.

Power-rate-distortion modeling for energy minimization of portable video encoding devices

In portable multimedia devices, one of the most critical issues is to minimize the energy consumption and thereby prolong the operational lifetime of the system while maintaining the required video quality. In this paper, we proposed a power-rate-distortion (P-R-D) model of video encoding system to maximize its lifetime. The proposed P-R-D model of video encoder is generated in two steps. The first step is the modeling process of the relationship between the power consumption and the distortion of video encoder. For this, we developed a power consumption model of a video encoder based on a power-scalable architecture of H.264/AVC encoder using the power consumption data of each functional module. The second step is generating the unified P-R-D model based on the P-D model and the conventional rate-distortion (R-D) model. Experimental results show that the proposed P-R-D model describes the relationship among power, rate, and distortion with 0.99 of the R-square value on the average.

Event statistics and criticality-aware bitrate allocation to minimize energy consumption of memory-constrained wireless surveillance system

An event criticality-aware wireless surveillance system tries to minimize the energy consumption by adjusting the image distortion (or quality) requirement according to event criticality. In this paper, we present a novel video encoding method which scales bitrate so as to minimize the energy consumption of the wireless surveillance system while satisfying the given memory constraint. Given event statistics, memory size, and distortion requirement, the presented method gives an energy-optimal bitrate based on an analytic formulation of energy-rate-distortion (E-R-D) relationship for the target system consisting of H.264 video encoder, event detector, transceiver and memory. Experimental results show that the proposed method offers up to 59.6% (29.1% on average) energy savings compared to an existing bitrate allocation method which does not consider event statistics [14].

A Dynamic Search Range Algorithm for Stabilized Reduction of Memory Traffic in Video Encoder

Embedded compression is commonly employed in a video codec to reduce the data traffic to/from off-chip frame memory. We proposed a method for maintaining the memory bandwidth requirement at a significantly reduced level through dynamic search range adjustment for the motion estimation based on the observed relationship between the compression ratio and the motion vector. This, together with the so-called “center moving” to adjust the newly incoming macroblocks, helped significantly lower the requirement of the memory bandwidth without a fluctuation. Experimental results have shown that the memory bandwidth requirement can be finally stabilized to 20% of that of the full search. The image quality degradation was merely 0.02 dB.

1.8mW, hybrid-pipelined H.264/AVC decoder for mobile devices

To meet the performance, area and power requirement constraints of H.264/AVC, we propose a hybrid pipeline architecture, and a data reuse mechanism to reduce off-chip memory access. A 4x4 sub-macroblock pipeline architecture is optimized for low power as well as performance. The proposed H.264/AVC decoder architecture can support CIF(352x288) 30 fps videos at 6MHz with 1.8 mW @ 1.65 V, implemented in 0.18 mum technology.

A low cost single-pass fractional motion estimation architecture using bit clipping for H.264 video codec

As the video resolution increases, high computational complexity of the fractional motion estimation (FME) introduces difficulty to meet real-time constraints in a video coding. In this paper, we proposed a single-pass FME algorithm and its architecture with low hardware cost and negligible loss of the image quality. The proposed algorithm directly searches only surroundings of both the predicted fractional motion vector and the search center. To reduce the hardware cost of processing units in the proposed FME architecture, bit clipping scheme is applied to processing units reducing the hardware cost by 25%. Experimental results show that the proposed algorithm provides almost the same rate-distortion performance as the full-search algorithm. The result of hardware implementation shows that a quad full high definition video (4096×2160) can be processed in real time (24 frame/sec) using 134k gates when the operating frequency is 250MHz. Compared with the recent work supporting quad full high definition video [8], the proposed FME architecture has shown 70% reduction of the hardware cost.

A High-Performance 2-D Inverse Transform Architecture for the H.264/AVC Decoder

In this paper, a high-performance 2-D inverse transform architecture for the H.264/AVC decoder is proposed. The proposed architecture utilizes the block multiplication and permutation matrices. By applying permutation matrices, the IDCT matrix is regularized and the inverse Hadamard transform is merged into IDCT with a minor modification. The proposed architecture eliminates the data transpose register array to make the 2-D direct transform possible with the minimum latency of one clock cycle. When comparing the proposed design with existing designs, the proposed design has over 22% higher throughput for computing IDCT and inverse Hadamard transform. It also owns over 62% higher hardware efficiency through the measure of DTUA for computing IDCT and inverse Hadamard transform.

A novel fast and low-complexity Motion Estimation for UHD HEVC

In this paper, we propose a novel fast and low-complexity Motion Estimation (ME) algorithm for Ultra High Definition (UHD) High Efficiency Video Coding (HEVC). Motion estimation occupies 77~81% of the amount of computation in HEVC. After all, the main key of codec implementation is to find a fast and low-complexity motion estimation algorithm and architecture. The proposed algorithm uses less than 1% of the amount of operations compared to full search algorithm while maintaining compression performance with slight loss of 1.1 (BDBR).

Analysis and complexity reduction of high efficiency video coding for low-delay communication

Bi-predictive motion compensation is an important coding tool in low-delay coding of HEVC. The proposed method reduces computational complexity about 30% by removing exhaustive bi-predictive motion estimation. The coding gain is about 6% in low-delay P coding.