Jongshin Shin

A Low-Jitter Added SSCG with Seamless Phase Selection and Fast AFC for 3rd Generation Serial-ATA

A low-jitter added 3GHz spread-spectrum clock generator (SSCG) with seamless phase selection and a fast automatic frequency calibration (AFC) was implemented in 90nm CMOS process. The proposed SSCG takes full advantage of multi-phase switching with increased sigma-delta operation speed. Large frequency shift and low jitter addition is obtained without extra phase management logic. A new AFC is also proposed for multi-band LC-VCO used in the SSCG. A fast and high resolution frequency calibration is done with direct counting of high frequency VCO clock. The experimental result shows that only 2.7ps peak-to-peak jitter is added by spread-spectrum clocking (SSC) and 400ns of unit frequency comparison time is achieved in AFC process

A 65nm 3.4Gbps HDMI TX PHY with supply-regulated dual-tuning PLL and blending multiplexer

A 65 nm HDMI TX PHY was designed with supply-regulated dual-tuning PLL and blending multiplexer. The proposed PLL uses a new dual-tuning scheme for small capacitor and low-jitter while keeping the supply regulation capability. A fractional-N operation for non-integer pixel clock generation was implemented with a blending multiplexer which enables seamless switching of high-speed multiphase clock. The fabricated PHY gives maximum 3.4 Gbps data rate per channel and shows 34 ps peak-to-peak data jitter.