Soo-Won Kim

Reduced Energy-Ratio Measure for Robust Autofocusing in Digital Camera

A robust and power efficient focus measure applicable in digital cameras is proposed. This measure, namely reduced energy-ratio (RER), uses the dc component and the lowest order five AC components of the discrete cosine transform (DCT) and is expressed as the ratio of the AC and DC components. The low-frequency AC and DC components contain the most energy (information) of an image as well as the detailed edge and base edge information. Autofocus score calculation method is used to assess the performance of the proposed measure and to compare it with other measures. Experimental results under various conditions verify the robustness of the proposed focus measure for the Gaussian as well as impulsive noises.

A low power consumption 10-bit rail-to-rail SAR ADC using a C-2C capacitor array

A 10-bit Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) for biomedical applications is presented. The proposed SAR ADC achieves rail-to-rail input range and low power consumption. A Digital-to-Analog Converter (DAC) using C-2C capacitor array and dynamic comparator is used for low power consumption. It is realized in 0.18 mum standard CMOS technology. This ADC has signal to noise and distortion ratios (SNDR) of 53.8dB for 1.5 V supply voltage. It consumes 13.4 muW at sampling rates of 137 kS/s.

Hand Biometric Recognition Based on Fused Hand Geometry and Vascular Patterns

A hand biometric authentication method based on measurements of the users hand geometry and vascular pattern is proposed. To acquire the hand geometry, the thickness of the side view of the hand, the K-curvature with a hand-shaped chain code, the lengths and angles of the finger valleys, and the lengths and profiles of the fingers were used, and for the vascular pattern, the direction-based vascular-pattern extraction method was used, and thus, a new multimodal biometric approach is proposed. The proposed multimodal biometric system uses only one image to extract the feature points. This system can be configured for low-cost devices. Our multimodal biometric-approach hand-geometry (the side view of the hand and the back of hand) and vascular-pattern recognition method performs at the score level. The results of our study showed that the equal error rate of the proposed system was 0.06%.

An anti-harmonic, programmable DLL-based frequency multiplier for dynamic frequency scaling

This paper describes a new delay-locked loop (DLL) based frequency multiplier which includes a lock controller and a PD to prevent false locking and increase locking range relative to conventional DLLs. By using multiple clock phase of the DLL, the lock controller detects whether the VCDL delay is within a correct locking range or not. A differentially controlled edge combiner for frequency multiplication is also proposed. The anti-harmonic DM-based frequency multiplier implemented in a 0.18 μm CMOS technology occupies an active area of 0.043 mm* and dissipates 36.7 mW at 1.7GHz. output clock. The measured RMS and peak-to-peak jitters for the multiplied output clock at 1.7GHz. are 2.64ps and 16.8ps, respectively.

A Single-Input Four-Output (SIFO) AC–DC Rectifying System for Vibration Energy Harvesting

An ac-dc rectifying system for vibration energy harvesting is proposed to generate outputs of four different voltage levels with a single power source. The proposed dual-output rectifier uses only four diodes, similar to a conventional single-output full-bridge rectifier. A switched-capacitor down-converter provides two output voltages from a single input from the voltage doubler by using the proposed load balancer with a low design complexity. The proposed system is implemented in a 0.35-μm CMOS process, and it occupies an area of 0.143 mm 2.

A CMOS TDC-based digital magnetic Hall sensor using the self temperature compensation

A CMOS TDC-based digital magnetic Hall sensor using the self temperature compensation schemes is proposed. The proposed sensor consists of the sensor device, its bias and signal-processing circuit which is fully compatible with a standard CMOS technology. For the high magnetic sensitivity, the MAGFET is implemented with proper geometric parameters. The TDC-based digital circuit is proposed for the low power consumption and easy design. The self temperature compensation schemes of mobility and threshold voltage temperature effects are utilized for the low temperature variation. The proposed sensor is implemented with a standard 0.18 mum CMOS technology and shows the good detectable resolution by 0.8 muT under magnetic fields ranging from 0 to 0.8 T and temperature variations by 250 nT ranging from -40degC to +80degC. And the very low power consumption by 360 muW at 1.8 V supply voltage is measured.

Efficient Discrete-Time Bandpass Sigma-Delta Modulator and Digital I/Q Demodulator for Multistandard Wireless Applications

This paper presents an efficient discrete-time bandpass sigma-delta (SigmaDelta) modulator and digital in-phase /quadrature (1/Q) demodulator for multistandard wireless applications. The proposed bandpass SigmaDelta modulator provides higher speed using advanced switched-capacitor resonators which are faster than the conventional ones. The test chip has been implemented in a 0.18 mum CMOS process and occupied with the active chip area ofO. 16 mm2. The power consumption of the fabricated chip is 2.34 mW with a 1.8 V supply voltage. The measured peak signal-to-noise ratios (SNR) are 34 dB for 1.536 MHz (T-DMB), 26 dB for 5 MHz (UMTS), and 20 dB for 10 MHz (WiBro) bandwidths, respectively. This paper also covers the simple and robust digital I/Q demodulator which has been realized using a field programmable gate array (FPGA) for digital signal processing.

A delay line with highly linear thermal sensitivity for smart temperature sensor

A highly linear thermal sensitivity delay line for smart temperature sensor is presented. The proposed delay line is a current starved inverter chain. A simple bias current source circuit is incorporated with the delay line to generate a current inversely proportional to temperature based on the transconductance characteristics of a MOS device at the vicinity of the zero temperature coefficient (ZTC) point. Simulation results in a 0.18 mum CMOS technology show that the proposed delay line has a higher linearity within 0.24degC in a wider temperature range from -40degC to 120degC compared with conventional structures.

Double precharge TSPC for high-speed dual-modulus prescaler

A double precharge TSPC D-flip-flop (DFF) is proposed and a 3 GHz dual-modulus prescaler using the double precharge TSPC in 0.35 /spl mu/m CMOS technology is presented in this paper. The double precharge TSPC DFF can reduce setup time compared with the conventional one, so it contributes to enhancing the operating speed of a dual-modulus prescaler. A 128/129 dual-modulus prescaler using the proposed flip-flop shows a maximum operating frequency of 3 GHz with 16 mW power consumption at 3.3 V power supply.

1.2-/spl mu/M non-epi CMOS smart power IC with four H-bridge motor drivers for portable applications

A smart power IC is designed with lateral DMOSFETs and fabricated in 1.2-/spl mu/m non-epi CMOS process. Since digitally controlled PWM scheme is utilized with a high-speed clock frequency, the designed smart IC is suitable for high-speed CD-ROM applications which require fast tracking and high-precision motor control. The smart power IC also combines a step-down DC-to-DC converter and a linear regulator which has a zero fold-back current capability. A self-isolated lateral DMOSFET cell with minimum process change is realized with a pitch size of 16 /spl mu/m which results to an extremely low specific on-resistance of 0.39 m/spl Omega/-cm/sup 2/. The active die area occupies 19.1 mm/sup 2/.