Jonne Poikonen

Current source calibration by combination selection of minimum sized devices

In this paper, we present an effective mismatch compensation method for analog current mode processing. Such a method is required in current and future mixed-mode processing systems, which take advantage of analog processing in addition to conventional digital logic. The proposed design utilizes analog processing devices that can be scaled down with the manufacturing process, therefore employing the advantages of CMOS technology in the form of a smaller implementation area. The range of input currents employed is 1 muA to 10 muA. The example circuit can be calibrated within 1 % of the nominal value at the 4sigma confidence interval with 65 mum2 of implementation area in 0.15mum CMOS technology

MIPA4k: Mixed-Mode Cellular Processor Array

This chapter describes MIPA4k, a 64 ×64 cell mixed-mode image processor array chip. Each cell includes an image sensor, A/D/A conversion, embedded digital and analog memories, and hardware-optimized grey-scale and binary processing cores. We describe the architecture of the processor cell, go through the different functional blocks and explore its processing capabilities. The processing capabilities of the cells include programmable space-dependent neighbourhood connections, ranked-order filtering, rank identification and anisotropic resistive filtering. For example, asynchronous analog morphological reconstruction operation can be performed with MIPA4k. The image sensor has an option for locally adaptive exposure time. Also, the peripheral circuitry can highlight windows of activation, and pattern matching can be performed on these regions of interest (ROI) with the aid of parallel write operation to the active window. As the processing capabilities are complemented with global OR and global sum operations, MIPA4k is an effective tool for high-speed image analysis.

Space-dependent binary image processing within a 64x64 mixed-mode array processor

This paper describes the binary (B/W) processing capabilities of a 64x64 mixed-mode array processor (MIPA4k). In addition to having space-independent weights (templates), the eight-connected B/W processing core is equipped with the option of space-dependent templates and bias. The template coefficients are 1-bit programmable, whereas the bias is programmable with two bits. The local templates and bias are stored in digital memories within the processing elements. These memories are accessible by the gray-scale processing cores of MIPA4k, making possible the setting of templates and bias based on the processing results of the gray-scale front-end. Alternatively, the coefficient circuits can be configured so that space-dependent weights are used, but, instead of letting the neighbor cells to control the coefficient circuits, the contents of the local memories can be used to control them. Therefore, 9-input threshold logic operations of the contents of local memory can be performed. This is useful in, e.g., identifying local binary patterns (LBP) in parallel. The realization of the B/W processing unit is described and selected measurement results of the 64x64 array are shown.

A gray-code current-mode ADC for mixed-mode cellular computer

Analog to digital converters are used in extremely many applications to convert real world signals into digital words. The converter presented in this paper, is designed for a cellular nonlinear network type system, where A/D converters are included in each cell to transform the gray scale value to be stored in a 6 bit SRAM memory bank. Because of this, the converter structure should have small silicon area, low power consumption and easy controlling. Presented ADC fulfills these requirements.

Towards Understanding the Formation of Uniform Local Binary Patterns

The research reported in this paper focuses on the modeling of Local Binary Patterns (LBPs) and presents an a priori model where LBPs are considered as combinations of permutations. The aim is to increase the understanding of the mechanisms related to the formation of uniform LBPs. Uniform patterns are known to exhibit high discriminative capability; however, so far the reasons for this have not been fully explored. We report an observation that although the overall a priori probability of uniform LBPs is high, it is mostly due to the high probability of only certain classes of patterns, while the a priori probability of other patterns is very low. In order to examine this behavior, the relationship between the runs up and down test for randomness of permutations and the uniform LBPs was studied. Quantitative experiments were then carried out to show that the relative effect of uniform patterns to the LBP histogram is strengthened with deterministic data, in comparison with the i.i.d. model. This was verified by using an a priori model as well as through experiments with natural image data. It was further illustrated that specific uniform LBP codes can also provide responses to salient shapes, that is, to monotonically changing intensity functions and edges within the image microstructure.

Rank identification for an analog ranked order filter

The paper suggests a method for rank identification from a previously reported programmable parallel current-mode analog ranked order filter circuit. This allows the input direction with any selected rank to be indicated as well as extracting the correct value from a set of input currents. The rank identification can be implemented with only O(n) increase in circuit complexity. This addition can be used to avoid errors caused by device mismatch and may also result in new application methods for the ranked order filter. Programmable ranked order filtering can be used for many image processing tasks such as mathematical morphology and median filtering.

An area-efficient full-wave current rectifier for analog array processing

The rectification operation is used in many nonlinear systems, such as those implementing fuzzy logic operations. This paper presents a very small current rectifier circuit which uses only three transistors to implement full-wave rectification. The low area-usage of the circuit allows it to be included in each processing cell of a large-scale, massively parallel, Cellular Nonlinear Network system, where the small area and low power consumption of building blocks is crucial. With the addition of current rectification, very efficient fuzzy processing functionality can be included in a grayscale CNN system.

Centroiding and classification of objects using a processor array with a scalable region of interest

In this paper we describe how the location and size of an object in a multi-object scene can be identified and classified using a processor array with a scalable region of interest. Objects of interest can be classified by matching them with 25-pixel object prototypes in a window that is adjustable from 17 x 17 to 5 x 5. Matlab simulations of the algorithms are shown. In order to carry out the operations effectively, the processor is equipped with a global OR and global sum. Also, the outputs of the row and column decoders can be determined by boundary cell outputs, in addition to the address bits. A 64 x 64-cell array has been sent to fabrication.

Online seam tracking for laser welding with a vision chip and FPGA enabled camera system

This paper presents the implementation of optical seam tracking for a laser welding process with parallel image processing on a smart camera. Real-time extraction of the seam location and direction is enabled by a combination of massively parallel focal plane processing on a Vision Chip and Hough-transform based analysis on an FPGA. The implementation of all analysis within a single embedded camera system offers low-lag control for correcting the path of a welding robot. The vision chip provides illumination adaptive image sensing and neighborhood based feature segmentation. To extract the dominant line from the segmented data, an auxiliary FPGA processor performs Hough analysis on the reduced binary data from the vision chip. The system can achieve a line extraction speed of more than 1000 fps, which enables real-time visual seam tracking and robot control. Evaluation results from on-line laser welding tests with processing performed on the camera system are reported in the article.

Solid-State Memcapacitors and Their Applications

This chapter introduces the concept of a memcapacitor, and reviews different approaches to its physical realization. Also, practical constraints for their usage are assessed. Because of their compatibility with traditional circuit integration technologies, two approaches are particularly interesting: the ferroelectric capacitor and the memcapacitor constructed by appending metal-insulator-metal (MIM) capacitor with a memristive switching layer. Ferroelectric capacitors have already been in use for many years so the properties of this technology are relatively well researched. The MIM-memristor hybrid structure can take advantage of the vital research on memristive memories. With sufficiently large ratio of the OFF and ON resistances of a memristive material, the compound structure behaves as a memcapacitive system. Finally, the potential of memcapacitors for memory and logic applications as well as for artificial neural networks are discussed.