Joo Hyung You

Effect of the trap density and distribution of the silicon nitride layer on the retention characteristics of charge trap flash memory devices

The trap distribution in the silicon-nitride layer, which was estimated by using experimental results, was used to clarify the retention characteristics of TaN-Al2O3-Si3N4-SiO2-Si (TANOS) memory devices. The dependence of the trap density and distribution of the silicon nitride layer on the retention characteristics in TANOS memory devices was investigated by using the two-coupled rate equations together with the Shockley- Reed statistics. Simulation results showed that the retention characteristics in TANOS memory devices increased with increasing trap density near and above the Fermi-level in the silicon-nitride layer. The simulation results for the retention characteristics of TANOS memory devices were in reasonable agreement with the experimental results. These observations can help improve understanding of the retention mechanisms and the reliability problems in charge trap flash (CTF) memory devices.

Dependence of Electrical Characteristics on the Depth of the Recess Region in the Scaled Tantalum Nitride–Aluminum Oxide–Silicon Nitride–Silicon Oxide–Silicon Flash Memory Devices

Nanoscale tantalum nitride–aluminum oxide–silicon nitride–silicon oxide–silicon (TANOS) memory devices utilizing a recess region were investigated to improve device performance and reduce cell-to-cell interference. The dependence of electrical properties on the depth of the recess region in the TANOS flash memory devices was simulated by using Synopsys TCAD Sentaurus. The cell-to-cell interference characteristics of the TANOS flash memory devices dependent on the recess region were investigated. The drain current at an on-state in the TANOS flash memory devices increased with increasing depth of the recess region owing to the existence of the fringe field generated from the recess region. The coupling ratio of the TANOS flash memory increased with increasing depth of the recess region. The simulation results showed that the cell-to-cell interference in the TANOS flash memory devices decreased with increasing depth of the recess region.

Decrease in Interference Effects between Cells for Metal–Oxide–Nitride–Oxide–Silicon NAND Flash Memory Devices with Metal Spacer Layers

Nanoscale metal–oxide–nitride–oxide–silicon (MONOS) NAND flash memory devices with a metal spacer layer were designed to increase the fringing field and the coupling ratio of the control gate and to decrease the interference effects between the cells. The simulation results showed that the drain current and the threshold voltage shift of the MONOS NAND flash memory devices utilizing a metal spacer increased owing to the increase in the fringing field and the coupling ratio. The electric field on the channel surface of the memory devices with a metal spacer layer increased, indicative of the achievement of the maximum fringing field effect, resulting in an increase in the drain current. The simulation results showed that the interference effects for the memory devices utilizing a metal spacer decreased resulting from the shielding of the electric field between neighboring cells.

Multibit Polycristalline Silicon?Oxide?Silicon Nitride?Oxide?Silicon Memory Cells with High Density Designed Utilizing a Separated Control Gate

Unique multibit NAND polycrystalline silicon–oxide–silicon nitride–oxide–silicon (SONOS) memory cells utilizing a separated control gate (SCG) were designed to increase memory density. The proposed NAND SONOS memory device based on a SCG structure was operated as two bits, resulting in an increase in the storage density of the NVM devices in comparison with conventional single-bit memories. The electrical properties of the SONOS memory cells with a SCG were investigated to clarify the charging effects in the SONOS memory cells. When the program voltage was supplied to each gate of the NAND SONOS flash memory cells, the electrons were trapped in the nitride region of the oxide–nitride–oxide layer under the gate to supply the program voltage. The electrons were accumulated without affecting the other gate during the programming operation, indicating the absence of cross-talk between two trap charge regions. It is expected that the inference effect will be suppressed by the lower program voltage than the program voltage of the conventional NAND flash memory. The simulation results indicate that the proposed unique NAND SONOS memory cells with a SCG can be used to increase memory density.

Nanoscale Two-Bit/Cell NAND Silicon–Oxide–Nitride–Oxide–Silicon Devices Designed on Fully Depleted Silicon-on-Insulator Substrates

Nanoscale 2-bit/cell NAND silicon–oxide–nitride–oxide–silicon (SONOS) memory devices with two separated control gates utilizing a fully depleted silicon-on-insulator (SOI) structure were designed. The program and erase characteristics of the proposed unique nanoscale 2-bit/cell NAND SONOS memory devices were simulated using technology computer-aided design tools. Simulation results showed that the leakage current in the subthreshold region and the subthreshold swing for the nanoscale 2-bit/cell NAND SONOS memory devices were decreased by utilizing a SOI structure. The initial threshold voltage of the nanoscale 2-bit/cell NAND SONOS memory devices with a SOI structure was larger than that of conventional SONOS devices without a SOI structure, indicative of a decrease in leakage current. Simulation results showed that the short-channel effects in the nanoscale 2-bit/cell NAND SONOS memory devices decreased in magnitude owing to a larger effective channel length.

Strain distributions and interband transitions of CdxZn1-xTe/ZnTe asymmetric double quantum dots with different degree of coupling

Strain distributions and interband transitions of CdxZn1−xTe/ZnTe asymmetric double quantum dots (DQDs) with different degree of coupling were calculated by using a three-dimensional finite difference method (FDM) taking into account strain and nonparabolicity effects. Bird’s-eye views of the truncated contour plots of the ground state wave functions at the conduction band of the Cd0.6Zn0.4Te/ZnTe DQDs showed the transition behavior from the coupling to the decoupling behaviors with increasing ZnTe spacer layer thickness. The interband transition energies from the ground electronic subband to the ground heavy-hole band (E1-HH1) in the CdxZn1−xTe/ZnTe DQDs, as determined from the FDM calculations, were in reasonable agreement with the experimental peaks of the temperature-dependent photoluminescence spectra corresponding to the (E1-HH1) interband transition energies in the temperature range from 32 to 130 K.

Enhancement of the device characteristics for nanoscale charge trap flash memory devices utilizing a metal spacer layer

Nanoscale charge trap flash (CTF) memory devices with a metal spacer layer were designed to decrease the interference effect and to increase the fringing field effect and the coupling ratio. The optimum metal spacer depth of the memory devices was determined to enhance the device performance of the memory devices. The drain current and the threshold voltage shifts of the CTF memory devices were increased due to an increase in the fringing field and the coupling ratio resulting from the existence of the optimized metal spacer. The interference effect between neighboring cells was decreased due to the shielding of the electric field resulting from the existence of the metal spacer layer.

Optical gains and interband transitions of CdTe/ZnTe single quantum wells

The optical gains of the CdTe/ZnTe single quantum wells with various CdTe widths were calculated by using a non-interacting pair Greens function and by an energy space integrated function. The interband transition energies from the ground electronic subband to the ground heavy-hole subband calculated taking into account optical gains were in qualitatively reasonable agreement with those determined from the PL spectra.

Interband transition energies and carrier distributions of CdxZn1−xTe/ZnTe quantum wires

Interband transition energies and carrier distributions of the CdxZn1−xTe/ZnTe quantum wires (QWRs) were calculated by using a finite-difference method (FDM) taking into account shape-based strain effects. The shape of the CdxZn1−xTe/ZnTe QWRs was modeled to be approximately a half-ellipsoidal cylinder on the basis of the atomic force microscopy image. The excitonic peak energies corresponding to the ground electronic subband and the ground heavy-hole band (E1-HH1) at several temperatures, as determined from the FDM calculations taking into account strain effects, were in qualitatively reasonable agreement with those corresponding to the (E1-HH1) excitonic transition, as determined from the temperature-dependent photoluminescence spectra.

Charging and discharging mechanims of vertically stacked Ni 1-x Fe x self-assembled nanoparticle arrays embedded in polyimide layers

Experimental and theoretical capacitance-voltage (C-V) curves for the Al/PI/multiple-stacked Ni1-xFex nanoparticle arrays/Pl/p-Si (100) structures at 300 K showed that the flatband voltage shift of the metal-insulator-semiconductor capacitor was affected by the value of the sweep voltage, indicative of the variations of the charged electron density in the multiple-stacked Ni1-xFex nanoparticle arrays. Experimental and theoretical current-voltage (I-V) results showed that the current increased with increasing applied voltage due to thermally assisted tunneling effect. Charging and discharging mechanisms of vertically stacked Ni1-xFex self-assembled nanoparticle arrays embedded in PI layers are described on the basis of the C-V and I-V results.