Keun Woo Lee

Effect of the trap density and distribution of the silicon nitride layer on the retention characteristics of charge trap flash memory devices

The trap distribution in the silicon-nitride layer, which was estimated by using experimental results, was used to clarify the retention characteristics of TaN-Al2O3-Si3N4-SiO2-Si (TANOS) memory devices. The dependence of the trap density and distribution of the silicon nitride layer on the retention characteristics in TANOS memory devices was investigated by using the two-coupled rate equations together with the Shockley- Reed statistics. Simulation results showed that the retention characteristics in TANOS memory devices increased with increasing trap density near and above the Fermi-level in the silicon-nitride layer. The simulation results for the retention characteristics of TANOS memory devices were in reasonable agreement with the experimental results. These observations can help improve understanding of the retention mechanisms and the reliability problems in charge trap flash (CTF) memory devices.

Change in the resistivity of Ge-doped Sb phase change thin films grown by chemical vapor deposition according to their microstructures

This study examined the effects of the composition and microstructure on the electric resistivity of Ge-doped Sb phase change thin films grown by cyclic plasma enhanced chemical vapor deposition. Ge and Sb layers were deposited sequentially to form either a GexSby mixture or Ge/Sb nanolaminated films. While the resistivity of the nanolaminated films was higher, the GexSby mixture showed a lower resistivity than the pure Sb film. This can be explained by the increase in carrier density of the alloy, as confirmed by first-principles calculations. An abrupt change in resistance accompanying a phase change was observed at ∼210 °C.

Optimization of control gate material and structure for enhancing 20nm 64Gb NAND flash reliability

We developed the new control gate (CG) material and structure in order to overcome scaling limitation beyond 20nm NAND flash cell. New CG material can achieve excellent gap-fill without void and improvement of the Gate CD Gap (GCG). And also, by using new CG material, CG depletion between floating gate (FG) can be improved. As a result, gate coupling ratio, bit-line (BL) interference and tail-cell Vt distribution are drastically improved. These technologies play an important role in the characteristic of scaled NAND flash memory cell and reliability.

Advanced Hot-Carrier Injection Programming Scheme for Sub 20nm NAND Flash Cell and beyond

A novel hot-carrier programming method for 20-nm-node technology NAND Flash cell is presented. In order to suppress the program disturb and the large power consumption, we utilized the self-channel boosting techniques with floated WLn-1, switching SSL, and a sufficiently high local field to cause efficient hot-carrier injection in NAND string. This method has been successfully demonstrated in the 20-nm-node NAND Flash cells, along with comprehensive studies on various bias conditions and algorithm. It would be very attractive for further scaling in NAND Flash memories beyond 20-nm technology.

Dependence of Electrical Characteristics on the Depth of the Recess Region in the Scaled Tantalum Nitride–Aluminum Oxide–Silicon Nitride–Silicon Oxide–Silicon Flash Memory Devices

Nanoscale tantalum nitride–aluminum oxide–silicon nitride–silicon oxide–silicon (TANOS) memory devices utilizing a recess region were investigated to improve device performance and reduce cell-to-cell interference. The dependence of electrical properties on the depth of the recess region in the TANOS flash memory devices was simulated by using Synopsys TCAD Sentaurus. The cell-to-cell interference characteristics of the TANOS flash memory devices dependent on the recess region were investigated. The drain current at an on-state in the TANOS flash memory devices increased with increasing depth of the recess region owing to the existence of the fringe field generated from the recess region. The coupling ratio of the TANOS flash memory increased with increasing depth of the recess region. The simulation results showed that the cell-to-cell interference in the TANOS flash memory devices decreased with increasing depth of the recess region.

Enhancement of the device characteristics for nanoscale charge trap flash memory devices utilizing a metal spacer layer

Nanoscale charge trap flash (CTF) memory devices with a metal spacer layer were designed to decrease the interference effect and to increase the fringing field effect and the coupling ratio. The optimum metal spacer depth of the memory devices was determined to enhance the device performance of the memory devices. The drain current and the threshold voltage shifts of the CTF memory devices were increased due to an increase in the fringing field and the coupling ratio resulting from the existence of the optimized metal spacer. The interference effect between neighboring cells was decreased due to the shielding of the electric field resulting from the existence of the metal spacer layer.