Joohyun Lee

A 159.2mW SoC implementation of T-DMB receiver including stacked memories

This paper describes a system on chip (SoC) implementation of terrestrial digital multimedia broadcasting (T-DMB) receiver which integrates RF tuner, analog to digital converter (ADC), baseband processor, and multimedia processor in single silicon wafer. The pseudo-SRAM (PSRAM) and SDRAM are doubly stacked with method of silicon in package (SIP). A low-IF RF tuner and a 10 bits pipelined ADC is used in this work as IP cores. Baseband processor contains Eureka-147 digital audio broadcasting (DAB) modem, MPEG1-Layer2 decoder, and outer decoder for T-DMB. Multimedia processor is consists of 32 bit embedded micro processor, 24 bit fixed-point DSP, and H.264/AVC hardware core. The T-DMB SoC was fabricated by using 0.13 um 1 poly 8 metal (1P8M) CMOS process and it gives successful performance of 159.2 mW total power dissipation including PSRAM and SDRAM at supply voltages of 1.2 V, 2.5 V for core and I/O respectively.

A mixed-radix pipeline FFT processor with trivial multiplications for LTE uplink

This paper presents a pipelined fast Fourier transform (FFT) processor consisting of radix-2, 3 and 5 for prime-sized discrete Fourier transform (DFT). The FFT processor does not require memory storing the twiddle factors or complex multiplications. It is adaptable for 34 kinds of the FFT length with a trivial multiplications and multiplexing of data in the LTE uplink. The proposed architecture reduces hardware complexity 32 %, and shows 737 Mbps throughput.

A Self-Biased Current-Mode Amplifier With an Application to 10-bit Pipeline ADC

This paper presents a self-biased current-mode amplifier (CMAMP) suitable for a switched-capacitor circuit. The CMAMP uses a subthreshold-biased transimpedance stage as a current-sensing load, and minimizes static power dissipation by passing bias current only at the input stage. The first-order system behavior with single dominant pole gives stable phase margin without complicated frequency compensation. Self-biasing circuits automatically generate bias voltages to sustain performance over a wide range of supply voltage. The designed CMAMP is verified in a 10-bit pipeline analog-to-digital converter (ADC) fabricated in a 65-nm CMOS process. The ADC achieves a figure of merit of 14.3 fJ/c-s with a supply voltage of 0.6 V at 2.5 MS/s.

Design of 256-point FFT processor for 100 Gb/s coherent optical OFDM system

This paper presents fully parallel fast Fourier transform (FFT) processor for coherent optical OFDM system. It has a length of 256. For processing of 100 Gb/s throughput it has parallel input and output structure. FFT processor has 32 radix-16 processor with trivial multiplication and consists of an array structure in parallel arithmetic processing. We designed and implemented the proposed FFT processor using Xilinx FPGA XCVU190. The result shows 205,530 LUTs and the maximum throughput is 46.592 Giga-Samples/sec.

Hardware design exploration of fully-connected deep neural network with binary parameters

This paper describes the exploration and analysis to design hardware of the fully connected deep neural network with binary weight value. The fully connected deep neural network is a promising reference model in order to implement fully hardwired classifier in mobile and IoT (Internet of Things) device. So, we analyzed its learning accuracy according to the number of layers and nodes through environment of reference simulation. And we analyzed hardware complexity and usage in terms of FPGA. We used Caffe framework to extract parameter and accuracy as reference model. We used Xilinx Vivado 2015.2 as synthesis tool for hardware design exploration.

Max-Min Energy-Efficiency Optimization in Wireless Powered Communication Network with Harvest-Then-Transmit Protocol

In this paper, we propose an energy-efficient transmission scheme for wireless powered communication networks with harvest-then-transmit protocol. Specifically, considering fairness among users, we present time resource allocation scheme to maximize the individual energy efficiency(EE) of each user, defined as a ratio of the user throughput to its harvested energy,based on the max-min criterion. EE optimization problem is highly non-convex and difficult to directly tackle. To solve this difficulty, we initially convert two EE problem into its equivalent parameterized subtractive form and, then, the corresponding optimal solution is determined via efficient two-layer iterative algorithm. The simulation results show that the proposed scheme provides better EE performances than those of the conventional schemes and the fairness-based algorithm considerably outperforms the other schemes in terms of the minimum user EE.

Energy efficiency optimization in multi-antenna wireless powered communication network

This paper proposes QoS-constrained energy-efficiency (EE) maximization scheme in a multi-antenna wireless powered network. Specifically, considering full CSI at the users, we optimize energy transmit covariance at the power transmitter, the power allocation at the users and the time allocation for energy and information transfer. The EE optimization problem is first converted into its equivalent parameterized subtractive form and, then, the corresponding optimal solution is determined via the Lagrange dual method. The performance of the proposed scheme is validated by simulation.

Face Recognition HW/SW IP implementation and validation for high reliability using a Virtual Platform

This paper presents design details of a Virtual Platform (VP) which is used for developing real time hardwired face recognition system. VP is promising technology to develop complex HW/SW system because it enables the simultaneous development of hardware and software. We have implemented a Virtual Platform and we used it for developing FPGA based face recognition system. The hardware portion is modeled with Transaction Level Model (TLM) in early phase of development. After hardware have been implemented, TLM model is substituted with real hardware system. The software is simultaneously developed with TLM hardware model and SW/HW integrity verification is seamlessly done by substituting TLM model with FPGA based real hardware. TLM model was efficient because it was much faster than RTL model and it can be seamlessly interfaced with SW development environment of virtual platform. FPGA based face recognition system was fully verified using application software running on virtual platform.

A fully-hardwired implementation of large vocabulary continuous speech recognizer

This article presents the hardware implementation of the speech recognition for real time performance and high-level accuracy. The stand-alone speech recognizer should simultaneously achieve the requirements, which are the low-latency performance and the low-power dissipation in an environment that cannot connect to the network. So, we made a speech recognizer as the hardware accelerator based on the hidden Markov model for reducing the load of the system processor without the cloud computing. Our overall design has the fully hardwired operation flow from the generation of the speech feature to the generation of the recognized words. Our design showed low-latency performance as the real time factor of 0.4 ~ 0.5 on FPGA, which operates at 100MHz operating frequency and uses the resource of 10%.

Fully hardwired illumination invariant face recognition engine and FPGA implementation

Face recognition system plays an important role in many applications such as surveillance, biometrics and security. In this paper, we present a FPGA implementation of real-time face recognition engine consists of face detection, eye detection and feature extraction/verification module. We apply Self-Quotient Image (SQI) to reduce illumination effect. Haar-AdaBoost trained classifiers are applied for face and eye detection. Linear Discriminant Analysis (LDA) and Discrete Cosine Transform (DCT) are used for face recognition. The complete system is implemented in a Xilinx Virtex-7 device. Experimental result shows that our face recognition system operates over 30 fps at 50MHz frequency for real-time applications.