Juyeob Kim

Performance analysis of NoC structure based on Star-Mesh Topology

The fabrication technology development of the semiconductor leads the evolutional design methodology to reconsider the efficiency, such as reusability and scalability. NoC (Network On Chip) is the remarkable alternative to support this trend that provides the interface between IPs. In this paper, the general performance analysis through considering the characteristic of the NoC was done with the proposed NoC topology. Besides, the performance at the topology which is the specification application, 4-channel H.264 decoder, was predicted in advance. We could build the environment facilitating the adjustment of the buffer size and mapping of IP with this scheme.

A mixed-radix pipeline FFT processor with trivial multiplications for LTE uplink

This paper presents a pipelined fast Fourier transform (FFT) processor consisting of radix-2, 3 and 5 for prime-sized discrete Fourier transform (DFT). The FFT processor does not require memory storing the twiddle factors or complex multiplications. It is adaptable for 34 kinds of the FFT length with a trivial multiplications and multiplexing of data in the LTE uplink. The proposed architecture reduces hardware complexity 32 %, and shows 737 Mbps throughput.

Star-Mesh NoC based multi-channel H.264 decoder design

In this paper we described the architectural exploration of Star-Mesh NoC based multi-channel H.264 decoder. The Star-Mesh NoC is comprised of local star switch and global mesh switch. By analyzing data transfers among the processors, IPs, and memories, we partitioned IPs into clusters to map then to Star-Mesh NoC architecture. In order to enhance data parallelism and NoC utilization, H.264 decoder IPs with much data traffic are mapped to star switch and shared memory is connected to mesh switch where star switch connected to mesh switch with 1-hop. We explored several mapping architecture to achieve improvement of the system throughput.

Hardware design exploration of fully-connected deep neural network with binary parameters

This paper describes the exploration and analysis to design hardware of the fully connected deep neural network with binary weight value. The fully connected deep neural network is a promising reference model in order to implement fully hardwired classifier in mobile and IoT (Internet of Things) device. So, we analyzed its learning accuracy according to the number of layers and nodes through environment of reference simulation. And we analyzed hardware complexity and usage in terms of FPGA. We used Caffe framework to extract parameter and accuracy as reference model. We used Xilinx Vivado 2015.2 as synthesis tool for hardware design exploration.

A fully-hardwired implementation of large vocabulary continuous speech recognizer

This article presents the hardware implementation of the speech recognition for real time performance and high-level accuracy. The stand-alone speech recognizer should simultaneously achieve the requirements, which are the low-latency performance and the low-power dissipation in an environment that cannot connect to the network. So, we made a speech recognizer as the hardware accelerator based on the hidden Markov model for reducing the load of the system processor without the cloud computing. Our overall design has the fully hardwired operation flow from the generation of the speech feature to the generation of the recognized words. Our design showed low-latency performance as the real time factor of 0.4 ~ 0.5 on FPGA, which operates at 100MHz operating frequency and uses the resource of 10%.

The hardware accelerator of the automatic speech recognition for the continuous Korean words

This paper describes the hardware of the speech recognition. The embedded speech recognizer should meet two conditions for the low-latency performance and the low-power dissipation. So, we made the fully-hardwired speech recognizer as the hardware accelerator to offload the system processor without the support of the remote computing environment. Our overall design was designed and implemented on FPGA board. Our design showed speedy response as the real time factor of 0.4 ~ 0.5 at 100MHz operating frequency and uses the HW resource of 10.