Bontae Koo

Cooperative jammer design in cellular network with internal eavesdroppers

In this paper, we consider a cooperative jammer to improve secrecy of the wireless transmission in a cellular downlink network. The private message intended for a single user should be kept from the remainder of the users who are regarded as internal eavesdroppers. To improve the secrecy of the intended user, we propose an employment of a helper with multiple antennas and design its optimal transmit beamforming vector. Specifically, the helper node generates the artificial interference to the internal eavesdroppers and so enhances the security by increasing the ambiguity at the eavesdroppers. Based on a framework of power gain region in [1], we optimize the transmission strategy for the helper which maximizes the secrecy capacity of the intended user. The analytical and simulation results show that the proposed scheme enhances the secrecy capacity. In addition, all users whose secrecy rates are zero with no helpers cooperation can achieve the positive secrecy rate by the proposed scheme.

Thermal sensor allocation and placement for reconfigurable systems

A dynamic monitoring of thermal behavior of hardware resources using thermal sensors is very important to maintain the operation of systems safe and reliable. This article addresses the problem of thermal sensor allocation and placement for reconfigurable systems. For programmable logic arrays, the degree of the use of hardware resources in the systems highly depends on the target application to be implemented, making the allocation of thermal sensors at the manufacturing stage inadequate (or too costly if implemented) due to the unpredictable thermal profile. This means that the thermal sensor allocation could be processed at the time when the reconfigurable logic is implemented (i.e., at the post manufacturing stage). This work proposes an effective solution to the problem of thermal sensor allocation and placement at the post-manufacturing stage. Specifically, we define the Sensor Allocation and Placement Problem (SAPP), and propose a solution which formulates SAPP into the Unate-Covering Problem (UCP) and solves it optimally. Also we combine SAPP with temperature correlation to reduce required sensors more aggressively and propose a solution by applying UCP again. We then provide an extended solution to handle a practical design issue where the hardware resources for the sensor implementation on specific array locations have already been used up by the application logic. Experimental results using MCNC benchmarks show that our proposed technique uses 62.4% and 19.7% less number of sensors to monitor hotspots on the average than that used by the grid-based and the bisection-based approaches while the overhead of auxiliary circuitry is minimized, respectively.

Adaptive Parallel and Iterative QRDM Algorithms for Spatial Multiplexing MIMO Systems

QR-decomposition with M-algorithm (QRDM) achieves quasi-ML performance in multiple-input multiple- output (MIMO) multiplexing systems. Nevertheless, QRDM per- forms avoidable computations because of its systematic search strategy and its unawareness of the channel and noise conditions. Another drawback is that QRDM has a sequential nature which limits the capabilities of pipelining. In this paper, we propose semi-ML adaptive parallel QRDM (APQRDM) and iterative QRDM (AIQRDM) algorithms based on set grouping. Using the set grouping, the tree-search stage of QRDM algorithm is divided into partial detection phases (PDP). Therefore, when the tree- search stage of QRDM is divided into 4 PDPs, the APQRDM latency is one fourth of that of the QRDM, and the hardware requirements of AIQRDM is approximately one fourth of that of QRDM. Moreover, simulation results show that in 4 × 4 system and at Eb/N0 of 14 dB, APQRDM decreases the average computational complexity to approximately 43% of that of the conventional QRDM. Also, at Eb/N0 of 0dB, AIQRDM reduces the computational complexity to about 54% and the average number of metric comparisons to approximately 10% of those required by the conventional QRDM and AQRDM.

Channel decoder architecture of OFDM based DMB system

We present the architecture and implementation of a channel decoder for a Korean standard DMB system. This channel decoder has many technical advantages of OFDM, error correction (Viterbi decoder and Reed-Solomon decoder) and audio source coding (MUSICAM). The channel decoder has a mixed hardware and software architecture to get a high performance and functional flexibility. It meets the requirements for a terrestrial DMB system. The prototype channel decoder of DMB system is developed using the DSP and FPGA hardware modules.

A pipelined low power architectural MPEG-4 video codec chip with deblocking filter for mobile wireless multimedia applications

We present a low-power MPEG-4 video codec chip capable of delivering high-quality video data in mobile wireless multimedia applications. The discussions focus on the architectural design techniques for implementing a high-performance and low power consumption video compression/decompression chip. By introducing partitioning of HW/SW modules, the efficiently optimized frame memory interface architecture, motion estimation skip scheme, and macroblock based pipeline deblocking filtering scheme, the proposed MPEG-4 video codec has low power consumption for mobile wireless multimedia application such as mobile phone, PDA and DMB. The proposed MPEG-4 video codec can perform 30 frames/s of QCIF or 7.5 frame/s of CIF at 27MHz with 128k-144kbps rates. Power consumption is 290mW and the chip size is 9.7mm × 9.7mm at 0.35 μm CMOS technology.We present a low-power MPEG-4 video codec chip capable of delivering high-quality video data in mobile wireless multimedia applications. The discussions focus on the architectural design techniques for implementing a high-performance and low power consumption video compression/decompression chip. By introducing partitioning of HW/SW modules, the efficiently optimized frame memory interface architecture, motion estimation skip scheme, and macroblock based pipeline deblocking filtering scheme, the proposed MPEG-4 video codec has low power consumption for mobile wireless multimedia application such as mobile phone, PDA and DMB. The proposed MPEG-4 video codec can perform 30 frames/s of QCIF or 7.5 frame/s of CIF at 27MHz with 128k-144kbps rates. Power consumption is 290mW and the chip size is 9.7mm t 9.7mm at 0.35 mm CMOS technology.

Implementation of baseband chip for the terrestrial digital multimedia broadcasting (T-DMB) system

A new national standard for terrestrial digital multimedia broadcasting (T-DMB) has been announced in Korea to provide high quality digital audio, video, and data broadcasting services to fixed, mobile, and portable receivers. We have developed an FPGA/ASIC implementation for the T-DMB system. The paper describes the features and functions of the newly developed T-DMB system. We also present the design, implementation, and performance of the baseband chip for the T-DMB system. The chip was fabricated using a 0.25 /spl mu/m 1P4M CMOS process.

MPEG-4 video codec for mobile multimedia applications

An MPEG-4 video codec (MoVa) has been developed for implementation of video coding applications according to 3G-324M. On 3G-324M, H.263 is mandatory and MPEG-4 is optional. However, MPEG-4 is proper for mobile multimedia applications (IMT-2000) by its error resilient and concealment tools. It can perform 30 frames/s of QCIF (SQCIF) or 15 frames/s of CIF at a maximum clock rate of 27 MHz for 128 kbps or 144 kbps. It meets the requirements for MPEG-4 SP@L2. A high bit rate and several sizes of video format are adequate for many applications, like videoconferencing, surveillance, news, or entertainment.

Efficient S-SCH Detection Algorithm for LTE Downlink Channel

The cell-search procedure in the long-term evolution (LTE) downlink includes the time synchronization, the frequency synchronization of frames, and the acquisition of cell identity (ID). This paper presents a low-complexity detection algorithm for a secondary synchronization channel (S-SCH) in the acquisition of cell ID. The proposed algorithm classifies total S-SCH sequences into subgroups based on the correlation among sequences, and thus, the number of correlators for S-SCH detection is significantly reduced. Despite the complexity reduction, the numerical results show that the proposed algorithm provides a comparable detection probability (DP) compared with existing low-complexity approaches. To verify the performance of the proposed algorithm, the complexity analysis and analytical derivation of the DP are also presented.

Transmit beamforming with imperfect CSIT in spectrum leasing for physical-layer security

In spectrum leasing, primary users (PUs) lease the part of their spectral resources to secondary users (SUs) in exchange for appropriate remuneration. In this paper, we consider spectrum leasing via cooperation for physical-layer security that the secondary cooperation exists for improving the primary secrecy rate while maintaining its quality of service (QoS). Unlike the previous researches with the perfect channel state information (CSI) at transmitter (CSIT) assumption, we study when no information regarding the eavesdropper is available at the transmitter. This imperfect CSIT makes the SUs transmission strategy limited. To find the optimal transmission technique for the SU, we formulate a problem appropriate for the imperfect CSIT case. By using the proposed problem, we design the optimal transmit beamforming for the SU. Also, we analyze the ergodic rate of the secondary link at high signal-to-noise ratio (SNR) when the secondary cooperation focuses only on maximizing the primary secrecy rate for the viable choice of the secondary QoS level. The numerical result shows that the primary secrecy rate by the proposed transmit beamforming is comparable to that based on the perfect CSIT.

A 159.2mW SoC implementation of T-DMB receiver including stacked memories

This paper describes a system on chip (SoC) implementation of terrestrial digital multimedia broadcasting (T-DMB) receiver which integrates RF tuner, analog to digital converter (ADC), baseband processor, and multimedia processor in single silicon wafer. The pseudo-SRAM (PSRAM) and SDRAM are doubly stacked with method of silicon in package (SIP). A low-IF RF tuner and a 10 bits pipelined ADC is used in this work as IP cores. Baseband processor contains Eureka-147 digital audio broadcasting (DAB) modem, MPEG1-Layer2 decoder, and outer decoder for T-DMB. Multimedia processor is consists of 32 bit embedded micro processor, 24 bit fixed-point DSP, and H.264/AVC hardware core. The T-DMB SoC was fabricated by using 0.13 um 1 poly 8 metal (1P8M) CMOS process and it gives successful performance of 159.2 mW total power dissipation including PSRAM and SDRAM at supply voltages of 1.2 V, 2.5 V for core and I/O respectively.