Joon-hee Lee

A 2.4-GHz Low-Power Low-IF Receiver and Direct-Conversion Transmitter in 0.18-

In this paper, a low-power low-IF receiver and a direct-conversion transmitter (DCT) suitable for the IEEE standard 802.15.4 radio system at the 2.4-GHz band are presented in 0.18-mum deep n-well CMOS technology. By using vertical NPN (V-NPN) bipolar junction transistors in the baseband analog circuits of the low-IF receiver, the image rejection performance is improved and the power consumption is reduced. In addition, by applying the V-NPN current mirrored technique in a DCT, the carrier leakage is reduced and the linearity performance is improved. The receiver has 10 dB of noise figure, -15 dBm of third-order input intercept point, and 35 dBc of image rejection. The transmitter has more than -2 dBm of transmit output power, -35 dBc of local oscillator leakage, and -46 dBc of the transmit third harmonic component. The receiver and transmitter dissipate 6 and 9 mA from a 1.8-V supply, respectively

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A manufacturable 2 Gb NAND flash memory with 0.044 /spl mu/m/sup 2/ cell size, which is the smallest cell size ever reported in semiconductor memory, is successfully developed with 90 nm NAND flash technology for high density file storage application. The three main key technology features of 90 nm NAND flash technology are advanced KrF lithography with off-axis illumination system equipped with a dipole aperture, reduced stack height of cell, and optimized gate reoxidation affecting tunnel oxide profile.

CMOS for IEEE 802.15.4 WPAN Applications

A new 1 Gb NAND flash technology with high-aspect-ratio floating gate, tungsten bit line and poly-Si source line has been developed. It is fabricated using 0.15 /spl mu/m photolithography, shallow trench isolation (STI), highly selective gate etching, damascene and chemical-mechanical polishing (CMP) processes. Since thick poly-Si is deposited and its sidewall has an inclined profile by anisotropic etching, narrow floating gate space (/spl sim/80 nm) under the design rule and a high coupling ratio (/spl sim/0.75) are obtained. To interconnect the NAND cell array, the poly-Si source is connected to every string as a common line and the tungsten bit line is damascened over the entire string. These double-layer interconnections lead to simple process and reduced steps. Thus, for the first time, a prototype 1 Gb NAND flash memory with an extremely small cell size of 0.11 /spl mu/m/sup 2/ has been achieved.

A 2 Gb NAND flash memory with 0.044 /spl mu/m/sup 2/ cell size using 90 nm flash technology

A fully planarized 16 Mb SOI DRAM has been successfully fabricated featuring pattern-bonded SOI (PBSOI), CMP processes, STI (Shallow Trench Isolation) and the silicon-on-capacitor (SOC) structure with 0.3 um technology using i-line lithography. The floating body effects of cell and peripheral SOI transistors are suppressed by the LIF (Local Implantation post Field oxidation) and halo implantation. The fully planarized process with SOC structure is established for multi-gigabit DRAM and embedded memory devices.

A 0.15 /spl mu/m NAND flash technology with 0.11 /spl mu/m/sup 2/ cell size for 1 Gbit flash memory

To meet ever-growing demands for higher mobile data-rates, LTE standards continue to evolve. While carrier aggregation (CA) improves data-rates, it requires wider aggregated signal bandwidth that limits the number of users that can be serviced. Techniques like 256QAM and 4×4 MIMO are attractive because improvements do not need wider signal bandwidth. To support 256QAM and 4×4 MIMO for the 5GHz band, we need IPN better than −48dBc or 155fsec rms. A digital fractional-N PLL that achieves 137fsec rms jitter integrating from 10kHz to 10MHz (or 142fsec 1kHz to 10 MHz) with a −78.6dBc near integer-N fractional spur is presented. We have introduced a TDC chopping technique, fine-conversion through SARADCs and TDC nonlinearity calibration to improve IPN and fractional spurs.

Advanced integration technology for a highly scalable SOI DRAM with SOC (Silicon-On-Capacitors)

A new string structure, having a cell-type string select transistor line (CT-SSL) is proposed for NAND flash memories beyond 20nm node device. The boosted potentials at a program-inhibited active line were measured with the CT-SSL and compared with the potential measured with a conventional SSL at 4Xnm, 2Xnm, and 1Xnm node devices. The boosted channel potentials were not degraded by drain-induced-barrier-lowering (DIBL) even when using one cell WL as a SSL. As-dopant diffused length by source/drain N+ implantation (S/D N+ IIP) was simulated to determine the minimum required gate length of a SSL. The newly proposed CT-SSL can successfully replace the conventional SSL.

24.8 A 14nm fractional-N digital PLL with 0.14ps rms jitter and −78dBc fractional spur for cellular RFICs

We investigate the effect of applying oxide spacer into MLC NAND flash memory with 63nm design rule. The oxide spacer is effective on reducing cell to cell coupling with its low-k dielectric constant. The uniform cell V/sub th/ distribution of 0.6V fulfilling the MLC operation is obtained while maintaining fast programming speed and sufficient cell current.

A New Cell-Type String Select Transistor in NAND Flash Memories for under 20nm Node

Digital PLL design challenges for cellular RFICs are presented. 5 digital PLLs are integrated in 28nm CMOS to support 3-Rx carrier aggregation (CA)/2-TxCA of FD-LTE/TD-LTE, GSM/EDGE, WCDMA/HSPA, and TD-SCDMA. The 400 kHz fractional spur of GSM/EDGE Tx LO is < −68 dBc for all channels. The integrated phase noise (IPN) degradation due to DCO-to-DCO coupling is < 0.5 dB even if two fractional PLLs are locked at same frequency.

Effect of low-k dielectric material on 63nm MLC (multi-level cell) NAND flash cell arrays

In this paper, digital-intensive analog circuits suitable for nano-scale CMOS process are presented for highly-digitized RF receivers. Unlike conventional RF receivers that use voltage-domain analog-to-digital converters (ADCs), we review the use of time-domain ADCs that employ delay cells and flip-flops, such as voltage-controlled oscillator (VCO)-based ADCs. Examples of VCO-based ADCs used in direct conversion receiver and direct RF sampling receiver will be presented, together with digital-intensive circuit techniques to implement high-order filtering. In addition, the techniques for the VCO nonlinearity is investigated.