Yoocheol Shin

A novel NAND-type MONOS memory using 63nm process technology for multi-gigabit flash EEPROMs

A NAND-type MONOS device has been successfully developed by breakthrough technologies including optimized cell structures and integration schemes providing favorable memory cell structures and peripheral circuits. In this study, optimized TANOS (TaN-Al2O 3-nitride-oxide- silicon) cells integrated using 63nm NAND flash technology showed high performance compatible to floating-gate (FG) cell. The newly-developed TANOS-NAND flash technology proved to be a promising candidate to replace FG memory beyond 50nm technology

Effects of Lateral Charge Spreading on the Reliability of TANOS (TaN/AlO/SiN/Oxide/Si) NAND Flash Memory

It was found that the charge loss behavior of TANOS (TaN-Al2O3-nitride-oxide-silicon) cells for NAND flash memory application is highly dependent on the gate structures for the first time. The gate structures with trap layers remained on source and drain regions showed increased charge loss compared to the one with trap layers separated between different gate lines. The improvement by removing the trap layers between gate lines suggests that the lateral charge spreading via trap layers from the programmed cells to the adjacent erased cells contributes to the charge loss of the TANOS cells.

Multi-Level NAND Flash Memory with 63 nm-Node TANOS (Si-Oxide-SiN-Al2O3-TaN) Cell Structure

For the first time, multi-level NAND flash memories with a 63 nm design rule are developed successfully using charge trapping memory cells of Si/SiO2/SiN/Al2O3/TaN (TANOS). We successfully integrated TANOS cells into multi-gigabit multi-level NAND flash memory without changing the memory window and circuit design of the conventional floating-gate type NAND flash memories by improving erase speed. The evolved TANOS cells show four-level cell distribution which is free from program disturbance and a charge loss of less than 0.4 V at high temperature bake test

A 64-Cell NAND Flash Memory with Asymmetric S/D Structure for Sub-40nm Technology and Beyond

A new 64-cell NAND flash memory with asymmetric S/D (Source/Drain) structure for sub-40nm node technology and beyond has been successfully developed. To suppress short channel effect in NAND memory cell, asymmetric S/D consisting of optimized junction and inversion layer induced by fringe field of WL bias which is applied at NAND operation conditions is successfully utilized. 64-cell NAND string which is double number of cells used in current NAND string is also used to further reduce bit cost by achieving over 10% chip size reduction while almost maintaining MLC (multi-level-cell) NAND performance requirements

Data Retention Characteristics of Nitride-Based Charge Trap Memory Devices with High-

The data retention characteristics of nitride-based charge trap memories using metal–oxide–nitride–oxide–silicon (MONOS) structures employing high-k dielectrics and high-work-function metal gates have been investigated. The fabricated MONOS devices with structures of TaN/Al2O3/Si3N4/SiO2/ p-Si show fast program/erase characteristics with a large memory window of greater than 6 V at program and erase voltages of ±18 V. From a bake retention test at high temperatures (200, 225, 250, and 275 °C), it is expected to take more than 40 years to lose less than 0.5 V charge loss at 85 °C. In this paper, we present an optimized cell structure for both improved data retention and erase speed, as well as a systematic study on the charge decay process in MONOS-type flash memory for high-density device applications.

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To realize TANOS-NAND flash memory, key requirements like program/erase speed, read retention, and program disturb window should be satisfied. In this work, we present 63 nm NAND-type TANOS cells to satisfy all the requirements and to replace floating-gate cells in conventional NAND flash memory without changing a circuit design and a sensing window

Dielectrics and High-Work-Function Metal Gates for Multi-Gigabit Flash Memory

In the proposed new scheme, which is named self aligned trap-shallow trench isolation (SAT-STI), such process damage on high-k layer can be minimized, achieving the goal of isolating the storage nitride layer successfully.

Charge Trapping Memory Cell of TANOS (Si-Oxide-SiN-Al2O3-TaN) Structure Compatible to Conventional NAND Flash Memory

Simultaneously formed Storage node contact and Metal contact Cell (SSMC) was investigated and developed with 0.18 /spl mu/m advanced KrF lithography as a promising candidate for the cell structure of 1 Gb DRAM and beyond, such as 4 Gb and 16 Gb DRAMs. SSMC can provide fast and reliable memory cell operation by reducing parasitic resistance between memory cell storage node and access transistor. Also SSMC can reduce the processing steps compared to the conventional COB (Capacitor Over Bit line) cell by forming storage node contact holes and metal contact hole at the same time. Furthermore, it is found that SSMC has many other advantages in terms of process margin, and wide application, for example in EML (embedded memory logic). Thus, SSMC is a promising cell structure for 1 Gb DRAM and beyond.

Self Aligned Trap-Shallow Trench Isolation Scheme for the Reliability of TANOS (TaN/AlO/SiN/Oxide/Si) NAND Flash Memory

A new 1 Gb NAND flash technology with high-aspect-ratio floating gate, tungsten bit line and poly-Si source line has been developed. It is fabricated using 0.15 /spl mu/m photolithography, shallow trench isolation (STI), highly selective gate etching, damascene and chemical-mechanical polishing (CMP) processes. Since thick poly-Si is deposited and its sidewall has an inclined profile by anisotropic etching, narrow floating gate space (/spl sim/80 nm) under the design rule and a high coupling ratio (/spl sim/0.75) are obtained. To interconnect the NAND cell array, the poly-Si source is connected to every string as a common line and the tungsten bit line is damascened over the entire string. These double-layer interconnections lead to simple process and reduced steps. Thus, for the first time, a prototype 1 Gb NAND flash memory with an extremely small cell size of 0.11 /spl mu/m/sup 2/ has been achieved.

Simultaneously formed storage node contact and metal contact cell (SSMC) for 1 Gb DRAM and beyond

The leakage current characteristics of the cobalt silicided NMOS transistors with a junction depth of 800 /spl Aring/ have been studied. In order to minimize the junction leakage current, the thickness of the CoSi/sub 2/ layer should he controlled under 300 /spl Aring/ and the Si surface damage induced by the gate spacer etch should be minimized. The post furnace annealing after the second silicidation by the rapid thermal annealing (RTA) process also affected the leakage current characteristics. The gate induced drain leakage (GIDL) current was not affected by the lateral encroachment of CoSi/sub 2/ layer into the channel direction when the gate spacer length was larger than 400 /spl Aring/.