Joon-Ho Choi

Elimination of false aggressors using the functional relationship for full-chip crosstalk analysis

As the portion of coupling capacitance increases in smaller process geometries, accurate coupled noise analysis is becoming more important in current design methodologies. We propose a method to determine whether aggressors can potentially switch simultaneously with the victim or not. The functional information is used to classify the aggressors. Our functional pruning algorithm inspects the conflict of the net states using CNF (conjunction normal form) and BDD (binary decision diagram). We present the experimental results on several industrial circuits. In the experiments, 6.4% of total aggressors are false and the accuracy of delay calculation can be improved up to 36.6%.

Analysis for complex power distribution networks considering densely populated vias

Due to the high speed and low power trends, the power distribution network (PDN) in multilayer printed circuit boards (PCBs) plays a pivotal role in terms of system performance. The paper presents an efficient analysis method for the irregularly shaped power/ground plane pair considering the effect of densely populated power/ground and signal vias in the frequency domain. The plane is divided based on geometric properties and modeled by the parallel-plate transmission line theory. For examination of various via effects, we have modeled vias according to their properties, such as power, ground and signal. Using a conventional circuit simulator, the input- and trans-impedance of power/ground planes are investigated. Since the proposed method is accurate as well as fast, it can be efficiently applied to multilayered PCB structures at the early design stage.

An efficient simultaneous switching noise analysis of high density multi-layer packages and PCBs considering the power and ground planes

In todays advanced semiconductor products, the width of the bus and the operating frequency increase. As a result, more simultaneous switching noise (SSN) is observed. However, SSN analysis requires the modeling of power and ground planes. The PEEC (Partial Element Equivalent Circuit) method is often used for modeling the planes but it suffers from a large amount of computation time and the limited size of PCB it can handle. This paper proposes a new fast method of generating an equivalent circuit networks for multi-layer packages and PCBs. A library of parasitics is built for different vertical structures and materials by using a electromagnetic field solver. This library is used to generate the equivalent circuit without the need for the complex field solving procedure. Compared to the conventional method (PEEC), the proposed method drastically reduces the time and effort for generating the equivalent circuit model with the same accuracy. This method has been used to design a variety of high speed memory module products.

A simultaneous switching noise analysis of a high speed memory module including the test environments and system-level models

As memory module products become more byte-wide and operate at higher speeds, more of the simultaneous switching noise (SSN) is observed. This paper presents SSN analysis results of high speed memory modules considering the power/ground planes and various interconnects of a test environment and computer system. Using the proposed model, highly accurate simulation results are obtained. Furthermore, we analyze the effect of SSN on the clock jitter and RAS Vil margin. The same model is also used to observe the effect of the decoupling capacitors on SSN. Based on our analysis, memory modules can be redesigned to increase the reliability.

A variable reduction technique for the analysis of ultra large-scale power distribution networks

In the trends of high density high speed and low power consumption, the analysis of power distribution networks is rapidly becoming an essential step in the design of high performance ICs. Nevertheless, the analysis is a great challenge, due to the large size of the networks. In this paper, we propose a variable reduction technique for the analysis of large-scale power distribution networks. The basic procedure of the proposed technique is reducing the power distribution network to a manageable size, solving the equation of the reduced network and then recovering the solutions of the original network. With the proposed variable reduction technique, we have achieved speed improvements up to several tens of times compared to the high performance linear system solution techniques, with no loss of accuracy.

A new fast and accurate method of extracting the parasitics of multi-layer packages

Due to the increase of portable and high performance integrated circuit (IC) applications, package designs get smaller and more complex. Chip scaled multi-layer IC packages become one of the solutions to accommodate such requirements. In the design environment for complicated packages, a fast and accurate interconnect parasitic extraction method is very important in order to explore alternative designs in a limited time and to cope with lacking of design margins. This paper proposes a novel interconnect parasitic extraction method which combines the advantages of the inherently fast 2D approach and accurate 3D approach. Thus, it efficiently models the 3D effects around traces and vias such as the variable shaped reference plane and shielding, chip placement, package fringes, and current flows. The speed and the accuracy of parasitic, extractions are substantially improved compared to the conventional method in the application of multi-layer packages for leading edge memory products.