Joon-Min Park

Photoresist Adhesion Effect of Resist Reflow Process

Making a sub-100 nm contact hole pattern is one of the difficult issues in the semiconductor process. Compared with another fabrication process, the resist reflow process is a good method of obtaining a very high resolution contact hole. However, it is not easy to predict the actual reflow result by simulation because very complex physics and chemistry are involved in the resist reflow process. We must know accurate physical and chemical constant values and many fabrication variables for better prediction. We made a resist reflow simulation tool to predict approximate resist reflow as functions of pitch, temperature, time, and array, among others. We were able to observe the simulated top view, side view, and changed hole size. We used the Navier–Stokes equation for resist reflow. We varied the reflow time, temperature, surface tension, and three-dimensional volume effect of our old model. However, photoresist adhesion is another very important factor that was not included in the old model. Thus, the adhesion effect was added on the Navier–Stokes equation, and such a case showed distinct differences in the reflowed resist profile and contact hole width from the case of the no adhesion effect.

32 nm Half Pitch Formation with High Numerical Aperture Single Exposure

According to the ITRS roadmap, DRAM half pitch (hp) will reach to 32 and 20 nm in 2012 and 2017 respectively. However, it is difficult to make sub-40 nm node by single exposure technology with currently available 1.35 numerical aperture (NA) ArF immersion lithography. Although it is expected to enable 32 nm hp with either double patterning technology or extreme ultra-violet lithography, there are many problems to be solved with cost reduction. Thus, the study of high-index fluid immersion technology should be pursued simultaneously. ArF water immersion systems with 1.35 NA have already introduced for 40 nm hp production. ArF immersion lithography using high-index materials is being researched for the next generation lithography. Currently, many studies are undergoing in order to increase NA with higher index fluid and lens in immersion technology. The combination of LuAG (n=2.14) and third-generation fluid could be used to make 1.55 NA. This combination with 0.25 k1, 32 nm hp can be obtained by single exposure technology. In order to check the realization of this process and to check the possible process hurdles for this high NA single exposure technology, 32 nm hp with 1:1 line and space patterning is tried. Various illumination conditions are tried to make 1:1 32 nm hp and the exposure and develop conditions are varied to check whether this single exposure can give processible window. As a result, 32 nm hp can be obtained by single exposure technology with 1.55 NA.

32 nm Half Pitch Formation with High-Numerical-Aperture Single Exposure

According to the International Technology Roadmap for Semiconductors (ITRS), memory half pitch (hp) will reach 32 and 20 nm by 2012 and 2017, respectively. However, it is difficult to fabricate a sub-40 nm node using single-exposure technology with the currently available 1.35-numerical-aperture (NA) ArF immersion lithography. Although it is expected that either double patterning technology or extreme ultraviolet lithography will enable the realization of 32 nm hp, there are still many problems that need to be solved regarding cost reduction. Thus, the study of high-index fluid immersion technology should be pursued simultaneously. ArF water immersion systems with 1.35 NA have already been introduced for 40-nm-hp production. ArF immersion lithography using high-index materials is currently being studied for next-generation lithography. Currently, many studies are being undertaken in order to increase NA for a high-index fluid and a lens in immersion technology. The combination of LuAG (n = 2.14) and a third-generation fluid could be used to realize 1.55 NA. This combination of 0.25k1 and 32 nm hp can be obtained using single-exposure technology. In order to determine the feasibility of this process and possible process hurdles for this high-NA single-exposure technology, 32 nm hp with a 1:1 line and space pattern is tested. Various illumination conditions are tested to realize 1:1 32 nm hp, and the exposure and development conditions are varied to determine whether this single exposure can provide a processible window. As a result, 32 nm hp could be obtained by single-exposure technology with 1.55 NA.

Patterning of 32 nm 1:1 Line and Space by Resist Reflow Process

Producing a sub-32 nm line and space pattern is one of the most important issues in semiconductor manufacturing. In particular, it is important to produce line and space patterns in flash memory-type devices because the unit cell is mostly composed of line and space patterns. The double patterning method is regarded as the most promising technology for producing a sub-32 nm half-pitch node. However, the double patterning method is expensive for the production and a heavy data split is required. In order to achieve cheaper and easier patterning, we propose a resist reflow process (RRP) for producing 32 nm 1:1 line and space patterns. In many cases, it is easier to produce a 1:3 pitch line and space pattern than a 1:1 pitch line and space pattern in terms of the aerial image, and RRP can transform a 1:3 pitch aerial image to a 1:1 resist image. We used a home-made RRP simulation based on the Navier–Stokes equation including the surface tension effect. Solid-E of Synopsis is used for the optical simulation, and electron-beam lithography is used for the experiment to verify the concept.

Critical Dimension Control for 32 nm Node Random Contact Hole Array Using Resist Reflow Process

A 50 nm contact hole (CH) random array fabricated by resist reflow process (RRP) was studied to produce 32 nm node devices. RRP is widely used for mass production of semiconductor devices, but RRP has some restrictions because the reflow strongly depends on the array, pitch, and shape of CH. Thus, we must have full knowledge on pattern dependency after RRP, and we need to have an optimum optical proximity corrected mask including RRP to compensate the pattern dependency in random array. To fabricate optimum optical proximity- and RRP-corrected mask, we must have a better understanding of how much resist flows and CH locations after RRP. A simulation is carried out to correctly predict the RRP result by including RRP parameters such as viscosity, adhesion force, surface tension, and location of CH. As a result, we obtained uniform 50 nm CH patterns even for the random and differently shaped CH arrays by optical proximity-corrected RRP.

Reduction of line width and edge roughness by resist reflow process for extreme ultra-violet lithography

Extreme ultra-violet lithography (EUVL) has been prepared for next generation lithography for several years. We could get sub-22 nm line and space (L/S) pattern using EUVL, but there are still some problems such as roughness, sensitivity, and resolution. According to 2007 ITRS roadmap, line edge roughness (LER) has to be below 1.9 nm to get a 22 nm node, but it is too difficult to control line width roughness (LWR) because line width is determined by not only the post exposure bake (PEB) time, temperature and acid diffusion length, but also the component and size of the resist. A new method is suggested to reduce the roughness. The surface roughness can be smoothed by applying the resist reflow process (RRP) for the developed resist. We made resist profile which has surface roughness by applying exposure, PEB and development process for line and space pattern. The surface roughness is calculated by changing parameters such as the protected ratio of resin. The PEB time is also varied. We compared difference between 1:1 L/S and 1:3 L/S pattern for 22 nm. Developed resist baked above the glass transition temperature will flow and the surface will be smoothed. As a result, LER and LWR will be much smaller after RRP. The result shows that the decreasing ratio of LER due to RRP is larger when initial LER is large. We believe that current ~ 5 nm LWR can be smoothed to ~ 1 nm by using RRP after develop.

Position Shift Analysis in Resist Reflow Process for Sub-50 nm Contact Hole

Contact hole (CH) patterning, especially for the sub-50 nm node, is one of the most difficult techniques in optical lithography. The resist reflow process (RRP) can be used to obtain smaller CHs. RRP is a simple technique in which the resist, after the development process, is baked above the glass transition temperature. Heating causes resist flow, and smaller CHs can be obtained. However, RRP is an unmanageable method because of the CH offset caused by the pattern position in random array CHs. Thus we tried optical proximity correction to find a uniform critical dimension (CD) for every CH, and we obtained uniform CDs for every CH after RRP. However, we still have a CH position shift problem. Because of the difference in the amount of resist that flows into the hole in a random array during the reflow process, position shift occurs. This position shift causes an overlay error, which may exceed the overlay error budget suggested in the ITRS roadmap. In this work, we try to determine not only uniform CD size of each CH, but also the optimum conditions for correcting CH position shift by homemade simulation. Moreover, we checked the behavior of CH position shift by e-beam lithography. Consequently, we confirmed that CHs shifted in a receding direction from each other, and obtained sub-50 nm CHs in a random array by considering the position shift by simulation and experiment.

Temperature and critical dimension variation in a single wafer on hot plate due to non-uniform heat source

Post exposure bake (PEB) is the most important process for chemically amplified resist to make nano-scale device. According to 2007 ITRS roadmap, critical dimension (CD) should be controlled below 1.9 nm on sub-22 nm half pitch in whole process of semiconductor. But CD error can be happened during the whole processes of exposure, PEB, develop, and etching. For this study, we assumed PEB process is just one of four processes, so that we take arithmetic mean error of four process, namely, ~ 0.5 nm (1.9 nm / 4) CD error should be controlled during PEB, even though PEB is the critical processes for CD control. 1 degree PEB temperature difference would make 3 nm CD change, so that we should control the temperature variation below 0.2 degree to control CD variation within 0.5 nm for 22 nm node. However, temperatures on the whole hot plate is not perfectly uniform. The temperature at the heat source is higher than that at the position with no heat source. Such a temperature difference inside hot plate would be directly transferred to the wafer and eventually inside the photoresist. Thus the temperature distribution inside the whole photoresist would be non-uniform, and this would make non-uniform CD distribution eventually. We calculated the temperature distribution within the hot plate in accordance with the position and structure of heat source. We also calculated the temperature distribution inside photoresist by considering the heat conduction. In addition to that, we estimated the possible CD variation caused by the non-uniform temperature distribution within photoresist on wafer.

Position shift analysis in resist reflow process for sub-50-nm contact hole

Contact hole (CH) patterning, specially for sub-50 nm node, is one of the most difficult technique in optical lithography. Resist reflow process (RRP) can be used to obtain smaller CH. RRP is a simple technique that the resist, after the develop process, is baked above the glass transition temperature (Tg). Heating causes the resist flowing, and we can obtain smaller dimension of CHs. However, RRP is unmanageable method because CH offset caused by pattern position in random array CH. So we tried OPC to find uniform CD for every CH, and we could obtain the uniform CD for every CH after RRP. However, we still have CH position shift problem. Because of a difference in an amount of resist that flow into the hole in random array during the reflow process, position shift occurs. This position shift makes overlay error, and it may exceed the overlay error limit suggested by ITRS roadmap. In this work, we try to find not only uniform CD size of each CH, but also optimum condition for correcting CH position shift by using home-made simulation. Moreover, we confirmed the tendency of CH position shift by e-beam lithography experiment. Consequently, we confirmed that CH moved to receding direction from each other, and obtained sub-50nm CHs in random array by considering the position shift through the simulation and experiment.

Resist Reflow Process for 32 nm Node Arbitrary Pattern

In order to decrease the size of contact holes, which is usually much larger than other patterns, the resist reflow process (RRP) has been widely used. Various types, shapes, and pitches of contact hole arrays are generated by RRP, but the use of RRP was limited to only contact hole patterns. The use of the same RRP method is expanded to 32 nm node arbitrary and complex patterns including dense line and space patterns. There might be simple one-dimensional patterns, but two-dimensional proximity conflict patterns are difficult to generate in general. In particular, the data split with proximity correction requires much attention for double patterning. 32 nm node arbitrary patterns could be generated using RRP without complex data splits when high-index fluid immersion lithography [numerical aperture (NA) 1.55] is used.