Heejun Jeong

Conduction mechanism of leakage current due to the traps in ZrO2 thin film

In this work, a metal-oxide-semiconductor capacitor with zirconium oxide (ZrO2) gate dielectric was fabricated by an atomic layer deposition (ALD) technique and the leakage current characteristics under negative bias were studied. From the result of current–voltage curves there are two possible conduction mechanisms to explain the leakage current in the ZrO2 thin film. The dominant mechanism is the space charge limited conduction in the high-electric field region (1.5–5.0 MV cm−1) while the trap-assisted tunneling due to the existence of traps is prevailed in the low-electric field region (0.8–1.5 MV cm−1). Conduction caused by the trap-assisted tunneling is found from the experimental results of a weak temperature dependence of current, and the trap barrier height is obtained. The space charge limited conduction is evidenced, for different temperatures, by Childs law dependence of current density versus voltage. Childs law dependence can be explained by considering a single discrete trapping level and we can obtain the activation energy of 0.22 eV.

Chirp Parameter of Electroabsorption Modulators with InGaAsP Intrastep Quantum Wells

The chirp parameter of electroabsorption modulators (EAMs) with intrastep quantum wells (IQWs) based on the InGaAsP material system is investigated theoretically. The chirp parameter of the IQW EAM, calculated by using the Kramers-Kronig relation, shows a discontinuity at a low voltage due to the blue shift in transition energy. Once the red shift is initiated, the chirp of the IQW EAM is similar to that of the conventional quantum-well (QW) EAM. Comparison with the conventional QW EAM shows that the IQW EAM could still be operated under high optical power without the compromise in chirp and absorption loss.

Investigation of Optimum Biasing and Undercut for Single Trench Alternating Phase Shift Mask in 193 nm Lithography

The use of an alternating phase shift mask is an effective method of improving resolution compared with binary and embedded attenuated phase shift mask technologies, but the intensity imbalance between the light propagating through the zero- and π-shifted spaces is the main obstacle to be overcome. Several technical methods are proposed to compensate for such an imbalance in the mask manufacturing process. The known general solutions for the intensity imbalance are applying a space bias and/or an undercut of the space region of the alternating phase shift mask. We evaluated the uniformity of the resist profile after the application of a space bias or an undercut of the mask space region in order to minimize the pattern position displacement and the critical dimension difference between the phase-shifted and unshifted regions for the 90 and 65 nm nodes. Additionally, we found that the imperfect side wall angle of an undercut or a space bias obviously affected the quality of pattern fidelity and hence investigated how the side wall angle affects pattern printability.

Chromeless Phase Lithography Using Scattering Bars and Zebra Patterns

Resolution enhancement technology refers to a technique that extends the usable resolution of an imaging system without decreasing the wavelength of light or increasing the numerical aperture (NA) of the imaging tool. Off-axis illumination and a phase shift mask (PSM) are essentially accompanied by optical proximity correction (OPC) for most devices nowadays. Chromeless phase lithography (CPL) is one of the PSM technologies. To obtain the best resolution, proper OPC is required with CPL. While the most common application of OPC is to provide mask bias, an additional technique is the use of scattering bars (SBs) and zebra patterns. We compared zebra patterns for 65 nm lines and spaces (L/S) and 45 nm isolated line (I/L) with SBs. To optimize zebra pattern density, we vary the line width and pitch of the zebra patterns. We confirmed that the use of SB and zebra patterns could realize the target linewidth and control necessary for acheiving dense L/S and I/L.

Position shift analysis in resist reflow process for sub-50-nm contact hole

Contact hole (CH) patterning, specially for sub-50 nm node, is one of the most difficult technique in optical lithography. Resist reflow process (RRP) can be used to obtain smaller CH. RRP is a simple technique that the resist, after the develop process, is baked above the glass transition temperature (Tg). Heating causes the resist flowing, and we can obtain smaller dimension of CHs. However, RRP is unmanageable method because CH offset caused by pattern position in random array CH. So we tried OPC to find uniform CD for every CH, and we could obtain the uniform CD for every CH after RRP. However, we still have CH position shift problem. Because of a difference in an amount of resist that flow into the hole in random array during the reflow process, position shift occurs. This position shift makes overlay error, and it may exceed the overlay error limit suggested by ITRS roadmap. In this work, we try to find not only uniform CD size of each CH, but also optimum condition for correcting CH position shift by using home-made simulation. Moreover, we confirmed the tendency of CH position shift by e-beam lithography experiment. Consequently, we confirmed that CH moved to receding direction from each other, and obtained sub-50nm CHs in random array by considering the position shift through the simulation and experiment.

32 nm 1:1 line and space patterning by resist reflow process

Making a sub-32 nm line and space pattern is the most important issue in semiconductor process. Specially, it is important to make line and space pattern when the device type is NAND flash memory because the unit cell is mostly composed of line and space pattern. Double patterning method is regarded as the most promising technology for sub-32 nm half-pitch node. However, double patterning method is expensive for the production and heavy data split is required. In order to make cheaper and easier patterning, we suggest a resist reflow process (RRP) method for 32 nm 1:1 line and space pattern. It is easier to make 1:3 pitch than 1:1 pitch line and space in terms of aerial image, and RRP can make 1:3 pitch aerial image to 1:1 resist image. We used home-made RRP simulation based on Navier-Stokes equation including surface tension effect. Solid-E is used for optical simulation, and e-beam lithography is used for the experiment to check the concept.

Optimization of chromeless phase mask by comparing scattering bars with zebra patterns

Resolution enhancement technology (RET) refer to techniques that extend the usable resolution of an imaging system without decreasing the wavelength of light or increasing the numerical aperture (NA) of the imaging tool. Off-axis illumination (OAI) and phase shift mask (PSM) are essentially accompanied with optical proximity correction (OPC) for most devices nowadays. In general, these three techniques do not work in isolation and the most aggressive mainstream lithography approaches use combinations of all RETs. In fact, OAI and PSM are essentially useless for typical chip-manufacturing applications unless accompanied by OPC. For low k1 imaging, strong OAI such as Quasar or dipole illumination types is the best. We used dipole illumination in this study. By using strong OAI, the amplitude of the 0th order is decreased and the amplitude of the 1st order is increased. Chromeless phase lithography (CPL) is one of PSM technologies and CPL mask is the possible solution for small geometry with low mask error enhancement factor (MEEF). CPL uses only 180 degrees phase-shifter on transparent glass without chromium film to define light-shielding region, destructive interference between light transmitted through the 0 degree and 180 degrees regions produces dark images. To obtain the best resolution, proper OPC is required with CPL. While the most common and straightforward application of OPC is to simply move absorber edges on the mask by giving simple mask bias, the interesting and important additional technique is the use of scattering bars. Also, we can use zebra patterns for the transmission control. Mask intensity transmission changes can impact the image quality. Zebra patterns are formed by adding chromium transverse features. The transmission will be controlled by the zebra pattern density. Technology node with ArF source is studied and the mask optimization is found to be a critical. And the linewidth of scattering bars, transmission (using zebra feature) are varied at line and space (L/S) patterns. We used 65 nm node 5 L/S and 45 nm node isolated line pattern. In order to optimize the zebra pattern density, we need to control the line width and pitch of the zebra patterns. For dense line and isolated line, the use of scattering bars and zebra patterns affected target critical dimension. We found out the better process window at dense 65 nm node by comparing the use of scattering bars with zebra patterns. Likewise, we optimized the isolated 45 nm node.