Joonhong Park

76–81-GHz CMOS Transmitter With a Phase-Locked-Loop-Based Multichirp Modulator for Automotive Radar

This paper presents the design of a linear frequency-modulated continuous-wave (FMCW) radar transmitter (TX) for automotive radar applications. The TX has a wide operating range from 76 to 81 GHz by employing a frequency-doubling architecture using an LC voltage-controlled oscillator operating at 38-40.5 GHz and a differential frequency doubler using a single transformer. A chirp generator is integrated into the TX, which provides various frequency chirp profiles with programmable chirp slope and sweep duration. The proposed CMOS FMCW TX can be applied to various modulation algorithms for multiple target detection and the avoidance of ghost targets. The TX is implemented using 65-nm CMOS technology. The chip size is 1.48 × 1.85 mm 2. The measurement results shows a 76-81-GHz frequency range and 3-dBm output power while dissipating 320 mW. The phase-noise density of the TX is -83.33 dBm/Hz at an offset frequency of 1 MHz when the output frequency is 77 GHz.

A CMOS centric 77GHz automotive radar architecture

A CMOS centric phase array radar architecture is proposed for long range detection with a high angular resolution and short range with a large field of view at once. And one channel transceiver is implemented in a 65nm CMOS technology and patch array antenna also fabricated on LTCC (Low Temperature Co-fired Ceramic) substrate for small form factor, low power radar. Measured 77GHz I/Q receiver showed a 22dB conversion gain with dynamic gain range of 76dB. Two kinds of VCO showed 69.6~81GHz and 75.2~79.2GHz tuning range. A gain of 14.3 dB and P1 dB of 10dBm is obtained at transformer coupled two-stage cascade power amplifier. All the measured results showed a good agreement with simulated one up to 110 GHz by modeling of passive/active test devices and EM (Electro Magnetic) simulations, and showed a the promising candidate for automotive radar applications.

A Fully-Differential Complementary Hartley VCO in 0.18

In this letter, a new complementary Hartley (C-Hartley) voltage controlled oscillator (VCO) with fully differential outputs is proposed, in which the self-biasing configuration is introduced to solve the biasing difficulty of a Hartley VCO by employing a five-port transformer. The proposed C-Hartley VCO with the center frequency of 5.6 GHz is implemented in a 1P6M 0.18 μm CMOS process. The measurement result shows that the phase noise is -123.6 dBc/Hz at 1 MHz offset frequency, while dissipating 6.5 mA from 1.6 V supply with the FOM of -188.5 dBc.

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This brief proposes two new types of current-reuse voltage-controlled oscillators (VCOs). One is a current-reuse Armstrong VCO (CR-AVCO) and the other is a complementary current-reuse Armstrong-Colpitts VCO (CR-ACVCO). Two one-transistor-based NMOS and PMOS AVCOs are combined into a complementary current-reuse form by sharing a transformer. The CR-ACVCO further improves the CR-AVCO by adding the Colpitts capacitive feedback, which has higher negative transconductance and, consequently, lower phase noise than that of the CR-AVCO. All the inductors are realized with one five-port transformer. The phase noise of the CR-AVCO and CR-ACVCO at 1-MHz offset frequency is -113.3 dBc/Hz at 4.84 GHz and -120.1 dBc/Hz at 5.3 GHz, respectively. The CR-AVCO and CR-ACVCO consume 2.32 and 2.74 mW from a 0.8- and 1.2-V supply, resulting in a high figure of merit with tuning range (FoMT) of -187.5 and -194.2 dBc/Hz, respectively. The proposed CR-VCOs are implemented in a 0.13 μm CMOS.

m CMOS Technology

The 77 GHz signal generator for an automotive radar application is presented. The circuit designed and fabricated using 65 nm CMOS technology. A 77 GHz signal is generated by the 38.5 GHz VCO and the frequency multiplier. Also, the signal generator with frequency dividers offers a 2.4GHz signal for external PLL lock. In order to obtain the target frequency against the PVT variation, a wideband VCO is designed with 2 bits capacitor array bank. And 2 stage injection locked dividers are designed with same oscillation core circuits except the inductor. The simulated signal generated output has output power of −5 dBm, current consumption of 100 mA and phase noise of −85 dBc/Hz at 1MHz offset frequency.

Transformer-Based Current-Reuse Armstrong and Armstrong–Colpitts VCOs

A 77GHz CMOS 4-channels receiver, transmitter with 3-outputs and array antenna architecture is proposed for low cost/small size automotive radar system, and implemented by using 65nm CMOS and LTCC substrate respectively. Measured performance of CMOS transceiver, which included useful functions such as dual operation of long/short range detection, I/Q signal process and gain attenuation when near target detection, shows comparable performances to that of commercial SiGe chips. Especially, the transmitter consumes one third lower power compared to SiGe chips. These results confirm that it may be a promising candidate for low cost and small size car radar system.

77 GHz signal generator with CMOS technology for automotive radar application

This paper presents a high efficient 13.56 MHz near field communication (NFC) transmitter in 0.18 µm CMOS process. A pulse width modulation (PWM) technique is employed to generate the ASK modulated output and to improve the transmitter efficiency. The proposed NFC transmitter can provide 0 ∼ 100% modulation depth in digital 6-bit accuracy. The multi-ASK modulation depth is realized by employing a delay locked loop (DLL), in which the modulation depth is controlled by the up and down charge pumping current ratio of the charge pump And the output current in the power stages is controlled by 6-bit digital codes for efficiency optimization.

A 77GHz CMOS array receiver, transmitter and antenna for low cost small size automotive radar

This paper presents a wideband and low-noise direct conversion front-end receiver supporting VHF and UHFbands simultaneously. The receiver iscomposed of a low-noise amplifier (LNA), a down conversion quadrature mixer, and a frequency divider by 2. The cascode configuration with the resistor feedback is exploited in the LNA to achieve a wide operating bandwidth. Four gainstep modesare employed using a switched resistor bank and a capacitor bank in the signal path to cope with wide dynamic input power range. The verticalbipolar junction transistors are used as the switching elements in the mixer to reduce 1/f noise corner frequency. The proposed front-end receiver fabricated in 0.18 μm CMOS technology shows very low minimum noise figureof 1.8 dB and third order input intercept pointof -12dBm inthe high-gain mode of 26.5 dBmeasured at 500 MHz.The proposed receiverconsumeslow current of 20 mA from a 1.8 V power supply.