Joonyoung Choi

Cu/SnAg Double Bump Flip Chip Assembly as an Alternative of Solder Flip Chip on Organic Substrates for Fine Pitch Applications

Recently, the need of fine pitch flip chip interconnection has been continuously growing. In spite of this trend, solder flip chip interconnections have reached the limit in fine pitch applications of less than about 150 mum pitch, because bump bridging between adjacent solder bumps occur. Therefore, the investigation on the fine pitch flip chip structure and its reliability are being needed. Metal column and solder double layered (^double bump) flip chip structure is one of the candidates for fine pitch applications. Double bump flip chip structure provides three advantages: (1) fine pitch flip chip interconnection less than 150 mum due to straight shape of metal column bumps, (2) better thermo-mechanical reliability by changing the height of metal column bumps, and (3) high current-carrying capability due to excellent electrical conductivity of Cu as one of the column bump materials. In this study, Cu (60 mum) / SnAg (20 mum) double bump flip chip were investigated as one of the promising fine pitch interconnections. We successfully demonstrated Cu/SnAg double bump flip chip assembly with 100 mum pitch on organic PCB substrates without bridged bumps by optimizing the bonding conditions such as bonding temperature profile, bonding force and flux. Assembled Cu/SnAg double bump joints had stable contact resistance of 12~14 mOmega. And then, we studied interfacial reactions and reliability evaluation of Cu/SnAg double bump flip chip assembly. Cu3Sn, Cu6Sn5, Ni3Sn4, (Cu,Ni)6Sn5, and Ag3Sn IMCs were formed at Cu/SnAg double bump joints after the additional reflow and solid-state aging. Excessive IMC growth and the formation of Kirkendall voids can be one of the origins which can deteriorate mechanical and electrical reliability of flip chip joints. All Cu/SnAg double bumps showed stable contact resistance after 1000 hours 85degC/85%RH test. And, Cu/SnAg double bumps generally maintained their initial contact resistance after high temperature storage test but showed slightly increased resistance at 150degC due to the formation of Kirkendall voids. On the other hand, contact resistance increased after thermal cycling test. After 1002 cycle T/C test, the failure at Si chip and bump interface was observed in corner and edge bumps. However, center bumps still maintained their contact even after 1000 T/C cycles. The main cause of thermal cycling failures was the Al and Ti UBM depletion between Si chip and Cu column bumps

Optimization of Compression Bonding Processing Temperature for Fine Pitch Cu-Column Flip Chip Devices

For the demand of high density input/output (I/O), fine-pitch, and low-k materials in copper column bump flip chip packages, Thermal Compression Bonding (TCB) with pre-applied Non Conductive Paste (NCP) has been developed in order to ensure manufacturing reliability. The narrow bonding process window of pre-applied NCP, short bonding time, and high bonding head temperature can cause low yield issues such as NCP voiding in solder and no solder wetting on substrate. For this reason, the bonding parameters, such as bonding temperature profiles and dwell times, have to be controlled and optimized to achieve good solder wettability. In this paper, the optimized maximum bonding temperatures and timing of the TCB process for fine pitch copper column flip chip package are examined. A thermal simulation is also conducted to correlate with experimental data. In the experiment, the bump temperature is measured with a thermocouple while the bonding head temperature and time are controlled with a heat controller. In the thermal simulation, a transient approach is used to consider the bonding temperature profiles and boundary conditions. The paper concludes with an approach and methodology to obtain optimized bonding temperature profiles which is crucial for the development of next generation fine pitch flip chip devices.

Advanced laminate carrier module warpage considerations for 32nm pb-free, FC PBGA package design and assembly

The trend in large body, high performance integrated circuit packaging for the 32 nm semiconductor node and beyond is towards low dielectric loss to enable high bandwidth / low loss channels, and low thermal expansion to protect fragile, ultra-low dielectric constant (k) chip dielectric materials from differential expansion stress. A low coefficient of thermal expansion (CTE), low dielectric loss laminate composite was developed using industry standard Sequential Build Up (SBU) fabrication techniques and novel laminate materials. This laminate technology was used in assembly of a Flip Chip Plastic Ball Grid Array (FC PBGA) module including a silicon test structure developed for 32 nm Custom Logic development. The same silicon test structure and laminate design were also used to fabricate modules using conventional high volume laminate materials. Various laminate physical parameters including composite CTE were determined. The warpage shape of each laminate was initially characterized at room temperature, and over the temperature range from 25°C to 240°C. Warpage of critical package features was measured and tracked throughout the various steps of the lead free flip chip module assembly process for multiple laminate cross sections, core and buildup materials. A quantity of assemblies of each type was built and measured, data is reported. Advantages and disadvantages of each laminate module type and implications for robust package assembly as evidenced by these results are discussed.

Studies on double-layered metal bumps for fine pitch flip chip applications

In this paper, Cu/SnAg double-layered bumps structure was proposed and investigated for the fine pitch flip chip applications. Test chip was designed considering the recent high speed memory device and its pad size and pitch was 60/spl mu/m and 100/spl mu/m, respectively. Cu and SnAg bumps were fabricated as a 60/spl mu/m and 20/spl mu/m thickness on SiO/sub 2//Ti/TiN/Al/TiW/Cu on Si wafer using the electroplating method. Test chip was flip chip assembled with PCB substrates using thermo-compression bonding method. Because the pitch was very tight, the flip chip bonding of Cu/SnAg double bumps was very difficult and it affected several bonding parameters such as bonding pressure, temperature, time, Cu bump diameter and so on. The bonding results were evaluated through the cross-sectional image of interconnection and the electrical continuity test of daisy chain and bump resistance using 4-point Kelvin structure. The long time reliability tests like thermal cycling test and 85/spl deg/C/85% test are now in progress after flip chip bonding and underfill dispensing.