Min-Suk Suh

High-Frequency Scalable Electrical Model and Analysis of a Through Silicon Via (TSV)

We propose a high-frequency scalable electrical model of a through silicon via (TSV). The proposed model includes not only the TSV, but also the bump and the redistribution layer (RDL), which are additional components when using TSVs for 3-D integrated circuit (IC) design. The proposed model is developed with analytic RLGC equations derived from the physical configuration. Each analytic equation is proposed as a function of design parameters of the TSV, bump, and RDL, and is therefore, scalable. The scalability of the proposed model is verified by simulation from the 3-D field solver with parameter variations, such as TSV diameter, pitch between TSVs, and TSV height. The proposed model is experimentally validated through measurements up to 20 GHz with fabricated test vehicles of a TSV channel, which includes TSVs, bumps, and RDLs. Based on the proposed scalable model, we analyze the electrical behaviors of a TSV channel with design parameter variations in the frequency domain. According to the frequency-domain analysis, the capacitive effect of a TSV is dominant under 2 GHz. On the other hand, as frequency increases over 2 GHz, the inductive effect from the RDLs becomes significant. The frequency dependent loss of a TSV channel, which is capacitive and resistive, is also analyzed in the time domain by eye-diagram measurements. Due to the frequency dependent loss, the voltage and timing margins decrease as the data rate increases.

Modeling and Analysis of Through-Silicon Via (TSV) Noise Coupling and Suppression Using a Guard Ring

In three-dimensional integrated circuit (3D-IC) systems that use through-silicon via (TSV) technology, a significant design consideration is the coupling noise to or from a TSV. It is important to estimate the TSV noise transfer function and manage the noise-tolerance budget in the design of a reliable 3D-IC system. In this paper, a TSV noise coupling model is proposed based on a three-dimensional transmission line matrix method (3D-TLM). Using the proposed TSV noise coupling model, the noise transfer functions from TSV to TSV and TSV to the active circuit can be precisely estimated in complicated 3D structures, including TSVs, active circuits, and shielding structures such as guard rings. To validate the proposed model, a test vehicle was fabricated using the Hynix via-last TSV process. The proposed model was successfully verified by frequency- and time-domain measurements. Additionally, a noise isolation technique in 3D-IC using a guard ring structure is proposed. The proposed noise isolation technique was also experimentally demonstrated; it provided -17 dB and -10dB of noise isolation between the TSV and an active circuit at 100 MHz and 1 GHz, respectively.

Joule Heating Effect on the Electromigration Lifetimes and Failure Mechanisms of Sn-3.5Ag Solder Bump

In this work, the effect of Joule heating on the electromigration lifetimes and damage evolution mechanism of Sn-3.5Ag flip chip solder bump was investigated at highly accelerated electromigration test conditions by using both ex-situ electromigration test in an oven and in-situ electromigration test in a scanning electron microscope, respectively. Highly accelerated electromigration test temperatures and current densities performed in this experiment were 140 ~ 175 degC, and 6 ~ 9times104A/cm2, respectively. Mean time to failure of solder bump decreased as the temperature and current density increased as expected. The activation energy and current density exponent were found to be 1.63eV and 4.6, respectively, which are very high due to severe Joule heating effect. In order to understand the fundamental failure mechanism and to investigate the current flow direction effect on the failure mechanism of Sn-3.5Ag solder bump, in-situ electromigration test was performed, which shows that interfacial crack initiated and propagated along Cu6Sn5/solder interface irrespective of current flow directions. Kirkendall voids formed at the Cu3Sn/Cu interface but, not related to the electromigration induced interfacial crack propagation. Current direction effect on the failure mechanism of Pb-free solder bump is also discussed.

Size effect on electromigration reliability of pb-free flip chip solder bump

To understand for size effect on electromigration behavior in flip chip Pb-free solder bump, electromigration tests were performed with change of pad open size and solder bump height at 140degC, 4.6times104 A/cm2. Electromigration lifetime increases with pad open size and bump height decreasing. In pad open size change, electromigration lifetime increase with pad open size increasing because applied current decrease with pad open size decreasing. In bump height change, electromigration resistance increase with bump height decreasing due to thermal gradient induced thermomigration effect decreasing. It seems to that electromigration resistance increase with size of solder bump decreasing.

Reliability challenges of through-silicon-via (TSV) stacked memory chips for 3-D integration: From transistors to packages

Recently, three-dimensional stacked chip package using through-silicon vias (TSVs) is a major paradigm which leads the transition of semiconductor technology from 2-D to 3-D IC in the electronic industry. However, lots of reliability concerns lie in the developing stage and we should clear away doubtful suspicion prior to mass production of 3-D stacked chip package. In this paper, an overview of reliability issues of 3-D TSV integration is introduced dividing into three categories: zero-level reliability of FEOL (front-end of the-line) such as transistors and capacitors, 1st level of BEOL (back-end of the-line) metallization and TSV interconnections, and 2nd level of micro-bumps of stacked chip interfaces. This paper describes the essential scope of the reliability challenges in 3-D IC packaging technology by dealing with reliability issues from transistor-level of the memory device to package micro-bump level of chip-to-chip interconnections.

Effect of Liner Oxide Densification on Stress-Induced Leakage Current Characteristics in Shallow Trench Isolation Processing

Controlling mechanical stress in the shallow trench isolation (STI) process is an increasing concern because it can affect circuit performance and yield. This paper presents the effect of liner oxide densification on the stress-induced junction leakage current in the STI process, compared to high density plasma (HDP) oxide densification before STI planarization. The simulation was performed for the trench isolation structure. It indicated that high temperature densification of the trench-tilled HDP oxide has a high probability of generating STI dislocations due to its inherently large mechanical stress and volume. The crystal defects and the mechanical stresses were significantly reduced by the introduction of liner oxide densification during STI processing; as a result, in the stress-induced junction, leakage characteristics were improved. The characteristics of standby current and column bit failure with regard to device yields have also been discussed.

Structure effects on the electrical reliability of fine-pitch Cu micro-bumps for 3D integration

Recently, flip chip solder bumps have been replaced by the fine-pitch solder micro-bump due to the miniaturization of electronic devices and the high performance requirement, and so on. Because of the fast decreasing size of the micro-bump and increasing power consumption needs in logic through-Si via applications, the significance of electromigration among major reliability issues have been increased. There are several important electrical current-induced reliability issues such as current crowding, polarity effect and thermomigration. And the excessive intermetallic compound (IMC) growth and Kirkendall voiding or micro voiding in micro-bump can degrade the mechanical reliability as well as electrical reliability. Therefore, the understanding of fundamental IMC growth mechanism is essential. This study systematically investigated the effects of bump structures such as solder height and UBM structure on the IMC growth kinetics and electromigration performance of Cu micro-bump. Quantitative analyses on the IMC growth kinetics during in-situ electromigration test were performed in a scanning electron microscope chamber under current stressing conditions with current density of 1.5 × 105 A/cm2 at 150°C. Under high temperature and electric current stressing, the IMCs growth is accelerated by electron wind force. And the IMC phase transition time became shorter because IMC growth rates increased. In Cu/Sn-Ag and Cu/Ni/Sn-Ag system, the effect of current crowding and Joule heating was negligible in fully IMC-transformed micro-bump. Finally, microvoid formation mechanisms during IMC growth in the Cu/Ni/thin Sn system were discussed in detail.

Effect of Joule Heating on Electromigration Characteristics of Sn-3.5Ag Flip Chip Solder Bump

Electromigration characteristics of Sn-3.5Ag flip chip solder bump were analyzed using flip chip packages which consisted of Si chip substrate and electroplated Cu under bump metallurgy. Electromigration test temperatures and current densities peformed were respectively. Mean time to failure of solder bump decreased as the temperature and current density increased. The activation energy and current density exponent were found to be 1.63 eV and 4.6, respectively. The activation energy and current density exponent have very high value because of high Joule heating. Evolution of Cu-Sn intermetallic compound was also investigated with respect to current density conditions.

Boron Transport Through Surface Channel pMOS Using W-poly Metal Gate Electrode Poly Si Doping Condition and Nitric Oxide Treatment Effects

This work considers boron transport through surface channel p-metal oxide semiconductors (pMOSs) using tungsten-poly metal gate electrode as a function of poly doping conditions and nitric oxide treatment by analyzing quasi-static capacitance-voltage curves and time-dependent dielectric breakdown characteristics obtained after applying the full thermal budget, especially including selective oxidation to prohibit tungsten oxidation. From the result obtained when nitrogen was implanted into undoped amorphous Si (α-Si), it can be recognized that out-diffusion of boron into tungsten and its nitride is negligible. Mixed implantations into undoped α-Si aggravates the gate depletion, whereas it has little relationship with boron penetration into the pMOS charnel. The abundance of dose in undoped α-Si facilitates the boron penetration, leading to gate oxide degradation and variation of the flatband voltage within the wafer as well as to the improvement of the gate depletion. From the comparison of the capacitance-voltage curve and the flatband voltage uniformity among experimental splits, it is found that the nitric oxide treatment retards the boron penetration into the pMOS channel effectively without significant degradation of the gate depletion.

Studies on double-layered metal bumps for fine pitch flip chip applications

In this paper, Cu/SnAg double-layered bumps structure was proposed and investigated for the fine pitch flip chip applications. Test chip was designed considering the recent high speed memory device and its pad size and pitch was 60/spl mu/m and 100/spl mu/m, respectively. Cu and SnAg bumps were fabricated as a 60/spl mu/m and 20/spl mu/m thickness on SiO/sub 2//Ti/TiN/Al/TiW/Cu on Si wafer using the electroplating method. Test chip was flip chip assembled with PCB substrates using thermo-compression bonding method. Because the pitch was very tight, the flip chip bonding of Cu/SnAg double bumps was very difficult and it affected several bonding parameters such as bonding pressure, temperature, time, Cu bump diameter and so on. The bonding results were evaluated through the cross-sectional image of interconnection and the electrical continuity test of daisy chain and bump resistance using 4-point Kelvin structure. The long time reliability tests like thermal cycling test and 85/spl deg/C/85% test are now in progress after flip chip bonding and underfill dispensing.