Joost Willemen

Avalanche Breakdown Delay in ESD Protection Diodes

Electrostatic discharge (ESD) protection diodes with a breakdown (BD) voltage above 50 V might exhibit a BD delay in the order of microseconds. The phenomenon is related to the low generation of seed carriers that can start an avalanche BD event by impact ionization. However, emission of carriers from deep traps, or the onset of tunneling generation, can shorten the delay to only fractions of a nanosecond. Emission from deep traps has been found strong enough to make this kind of device effective for protection under standard ESD conditions. However, the application of a bias voltage prior to a stress pulse empties the trap states and thus leads to increasing BD delay. This paper investigates the BD delay in an ESD protection diode under various bias and pulse conditions. A model for the BD delay is proposed, taking into account the different seed carrier generation mechanisms. The activation energy of the dominating deep trap can be calculated to 0.18 eV by measuring the time to BD at different temperatures.

Avalanche Breakdown Delay in High-Voltage p-n Junctions Caused by Pre-Pulse Voltage From IEC 61000-4-2 ESD Generators

Electrostatic-discharge (ESD) tests with IEC 61000-4-2 generators are often performed at component level but are known to suffer from poor reproducibility. In this paper, it is shown that IEC 61000-4-2 generators can charge the tested device to several tens of volts before the actual ESD pulse is applied. This pre-pulse voltage (PPV) can lead to delayed avalanche breakdown (BD) initiation in silicon junctions. The origin of the BD delay is the emptying of deep trap states within the space-charge region, which lowers the contribution to the generation current due to carrier emission from the deep states. The BD delay is critical for ESD protection devices and can also lead to a dramatic reduction of the snapback trigger current in DMOS transistors. However, transient gate turn-on of the DMOS transistor eliminates the BD delay and can thus increase the ESD robustness. It is shown that the PPV varies strongly between commercial IEC generators, and it is proposed that this could be one of the main reasons for the poor reproducibility of IEC tests. A newly proposed method to deliver an IEC 61000-4-2-shaped pulse through a 50-¿ transmission line is investigated with respect to the correlation with real IEC generators. It is shown that PPV-related issues are not addressed by this method, unless an additional bias voltage is applied during the test. It is also demonstrated that PPV is existent in real-world IEC discharges and must not be neglected for component qualification.

Gain-product in pnpn-structures at high current densities and the impact on the IV-characteristic

Pnpn-structures show a sudden increase in on-state clamping voltage due to insufficient gain product of their internal BJTs at high current densities. This can be described with bipolar theory and high-current effects. High-current IV characteristics confirm a gain product decrease and critical current densities are extracted from two terminal pnpn-structures.

Transient voltage suppressors—technologies and characteristics

Transient voltage suppressors (TVS) are widely used for electrostatic discharge (ESD) and surge protection of electronic devices. Especially the usage of mobile devices for wireless communications requires extremely high production quantities in the range of multi-billion pieces of TVS per year. This article gives an introduction to the key performance parameters of different TVS technologies with low parasitic capacitance in the picofarad and sub-picofarad range, such as gas discharge tubes (GDT), polymer voltage suppressors (PVS), multi-layer varistors (MLV) and silicon TVS.ZusammenfassungTransient Voltage Suppressors (TVS) werden weitverbreitet zum ESD-Schutz sowie zum Überspannungsschutz von elektronischen Produkten eingesetzt. Speziell die stark wachsende Anwendung von Mobiltelefonen erfordert extrem hohe Fertigungsvolumen von ESD-Schutzbauelementen in Multi-Milliarden-Stückzahlen pro Jahr. Dieser Artikel gibt eine Einführung in die wichtigsten elektrischen Parameter von ESD-Schutzbauelementen sowie verschiedenen Technologien mit geringster parasitärer Kapazität im Picofarad- und Sub-Picofarad-Bereich. Es werden miniaturisierte Gasentladungs-Röhren (GDT), Polymer-ESD-Schutzbauelemente (PVS), Mehr-Lagen-Varistoren (MLV) und Silizium-TVS-Bauelemente beschrieben sowie deren typische Eigenschaften gezeigt.

Simulation and modelling of VDMOSFET self protection under TLP-stress

Abstract We present a simple and practical model for modelling the electrical behaviour of scalable vertical diffused MOSFETs (VDMOSFETs) under TLP stress. The trigger current is found to be dependent from gate–source voltage and geometry. A scalable model for analog circuit simulation is developed. As application example, self protection of VDMOS in resistive coupled gate configuration is investigated. For this purpose the device behaviour under TLP stress is modelled. The model is shown to predict VDMOS self protection under TLP stress for a wide range of geometries in an excellent way. A comprehensive analytical model calculation is added which explains the range of model validity. Within this range maximum HBM rating of the resistive gate coupled devices is predicted correctly.