Ulrich Glaser

Automotive 130 nm smart-power-technology including embedded flash functionality

In this paper a 130 nm BCD technology platform is presented. The process offers logic-devices, flash-devices and high voltage devices with rated voltages up to 60 V. There are HV analog devices with variable channel length and HV power devices with low on-resistances. To ensure the safe operation of the power devices, a superior robustness against high energetic pulses of different length and repetitions could be achieved. The isolation of the different voltage stages is ensured by deep trenches and highly doped buried layers.

Development strategy for TLU-robust products

Detailed transient latch-up (TLU) analyses of external test structures show that a DC trigger does not necessarily reflect worst case conditions. Furthermore, the classical guard ring latch-up protection approach fails for transient trigger. In this contribution, design recommendations for TLU-safe designs are presented. The knowledge about the perturbation environment and an appropriate design are essential for a TLU-robust product.

A failure levels study of non-snapback ESD devices for automotive applications

Snapback ESD devices suffer from increasing danger when the protected ICs experience ESD events in powered up states. To ensure more reliable ESD protections, non-snapback ESD structures are gaining more importance in the field of automotive ESD design. Two types of on-chip non-snapback ESD devices, pn-diodes and active FET structures are investigated in this work regarding their failure levels. Characteristics of the ESD devices as well as electrical SOA of an nLDMOS are evaluated and discussed in detail with TCAD electro-thermal simulation, SPICE circuit simulation and mainly TLP measurements. Comparison of the efficiency of different ESD protections considering ESD window is also given, delivering the basic idea of choosing the right ESD devices in automotive applications.

Base pushout driven snapback in parasitic bipolar devices between different power domains

Modern integrated circuits still exhibit unexplored ESD failure modes. In this work, the trigger voltage of the base pushout driven snapback in parasitic bipolar devices is identified as a limiting value for the ESD concept design and the cause for damage in a 0.13 /spl mu/m technology. Its strong dependence on base control by standard ESD protection elements is considered carefully. Effective countermeasures on circuit and device design level are examined by thermo-electrical device simulations and theoretical estimations.

Novel Active ESD Clamps for High-Voltage Applications

Large power MOS transistors (bigMOS) have potential electrostatic discharge (ESD) protection capabilities and are often used in actively controlled ESD clamps. In high-voltage and especially automotive applications ranging typically from 10 to 100 V operation voltage, statically triggered active ESD clamps are often used due to their false triggering safety. This paper presents novel statically triggered active ESD clamps, which rely on advanced trigger circuits optimizing the gate control of the bigMOS. With enhanced tailoring to the application requirements, the active ESD clamps substantially improve clamp area efficiency and significantly reduce ESD window requirements.

Avalanche Breakdown Delay in High-Voltage p-n Junctions Caused by Pre-Pulse Voltage From IEC 61000-4-2 ESD Generators

Electrostatic-discharge (ESD) tests with IEC 61000-4-2 generators are often performed at component level but are known to suffer from poor reproducibility. In this paper, it is shown that IEC 61000-4-2 generators can charge the tested device to several tens of volts before the actual ESD pulse is applied. This pre-pulse voltage (PPV) can lead to delayed avalanche breakdown (BD) initiation in silicon junctions. The origin of the BD delay is the emptying of deep trap states within the space-charge region, which lowers the contribution to the generation current due to carrier emission from the deep states. The BD delay is critical for ESD protection devices and can also lead to a dramatic reduction of the snapback trigger current in DMOS transistors. However, transient gate turn-on of the DMOS transistor eliminates the BD delay and can thus increase the ESD robustness. It is shown that the PPV varies strongly between commercial IEC generators, and it is proposed that this could be one of the main reasons for the poor reproducibility of IEC tests. A newly proposed method to deliver an IEC 61000-4-2-shaped pulse through a 50-¿ transmission line is investigated with respect to the correlation with real IEC generators. It is shown that PPV-related issues are not addressed by this method, unless an additional bias voltage is applied during the test. It is also demonstrated that PPV is existent in real-world IEC discharges and must not be neglected for component qualification.

Transient interferometric mapping of carrier plasma during external transient latch-up phenomena in latch-up test structures and I/O cells processed in CMOS technology.

Substrate current distribution as trigger for external latch-up (LU) and transient latch-up (TLU) is analyzed by optical transient interferometric mapping (TIM) technique. The transient free carrier (plasma) concentration related to substrate current flow is studied for various guard-ring configurations and injection carrier type on special test structures and real I/O cells. TIM uncovers proximity effects in I/O cells causing substrate current crowding which are important for the definition of effective LU protection concepts.

Active clamp design for on-chip GUN protection

On-chip active clamps show attractive performance for the component-level ESD protection like HBM, but suffer usually from their weakness for short-pulse and high-current events like the first peak of IEC 61000-4-2 (GUN) pulses. This disadvantage can be overcome by adequate active clamp design, resulting in an area efficient active clamp GUN protection.