David Johnsson

Nonlinear dynamics approach in modeling of the on-state-spreading - related voltage and current transients in 90nm CMOS silicon controlled rectifiers

Using a theory of front propagation in nonlinear active media we model the on-state spreading related voltage, current and on-state width transients in 90nm CMOS silicon controlled rectifiers. The model explains well voltage transients during the rising edge of ESD pulses and predicts a non-trivial dependence of device voltage on number of triggering regions.

On the Electrostatic Discharge Robustness of Graphene

A comprehensive study of electrostatic discharge (ESD) characterization of atomically thin graphene is reported. In a material comprising only a few atomic layers, the thermally destructive second breakdown transmission line pulsing (TLP) current (It2) reaches a remarkable 4 mA/μm for 100-ns TLP and ~8 mA/μm for 10-ns TLP or an equivalent current density of ~3 × 108 and 4.6 × 108 A/cm2, respectively. For ~5-nm thick (~15 layers) graphene film, It2 reaches 7.4 mA/μm for 100-ns pulse. The fact that failure occurs within the graphene and not at the contacts indicates that intrinsic breakdown properties of this new material can be appropriately characterized using short-pulse stressing. Moreover, unique gate biasing effects are observed that can be exploited for novel applications including robust ESD protection designs for advanced semiconductor products. This demonstration of graphenes outstanding robustness against high-current/ESD pulses also establishes its unique potential as transparent electrodes in a variety of applications.

Measuring Holding Voltage Related to Homogeneous Current Flow in Wide ESD Protection Structures Using Multilevel TLP

Due to the negative-differential-resistance-related instability, the current-density distribution in sufficiently wide devices exhibiting S-shaped <i>I</i>-<i>V</i> characteristics becomes inherently inhomogeneous along the device width. High-current-density on-state (i.e., a current filament) and low-current-density off-state regions are spontaneously formed, leading to the formation of a vertical branch in the <i>I</i>-<i>V</i> curve at a so-called coexistence voltage <i>u</i>_CO. In electrostatic discharge (ESD) protection devices (PDs), this vertical <i>I</i>- branch usually determines the lowest voltage point that can be accessed by a conventional transmission line pulser (TLP). However, the real holding point of device <i>VH</i>, which is related to an <i>I</i>-<i>V</i> part with a homogeneous current distribution, lies below <i>u</i>_CO, i.e., <i>VH</i> <; <i>u</i>_CO. Here, we present a method on how to determine <i>VH</i> and the <i>I</i>-<i>V</i> branch below <i>u</i>_CO, which is “hidden” when using a conventional TLP analysis. We use a multilevel TLP system and demonstrate it on a 90-nm technology silicon-controlled rectifier ESD PD. Measurement considerations, which take into account the finite speed of the on-state spreading effect and the self-heating effect, are discussed. Implications relevant for latch-up prevention and for the comparison of experiments with 2-D and 3-D technology computer-aided design simulations are also given.

Avalanche Breakdown Delay in ESD Protection Diodes

Electrostatic discharge (ESD) protection diodes with a breakdown (BD) voltage above 50 V might exhibit a BD delay in the order of microseconds. The phenomenon is related to the low generation of seed carriers that can start an avalanche BD event by impact ionization. However, emission of carriers from deep traps, or the onset of tunneling generation, can shorten the delay to only fractions of a nanosecond. Emission from deep traps has been found strong enough to make this kind of device effective for protection under standard ESD conditions. However, the application of a bias voltage prior to a stress pulse empties the trap states and thus leads to increasing BD delay. This paper investigates the BD delay in an ESD protection diode under various bias and pulse conditions. A model for the BD delay is proposed, taking into account the different seed carrier generation mechanisms. The activation energy of the dominating deep trap can be calculated to 0.18 eV by measuring the time to BD at different temperatures.

Second breakdown behavior in bipolar ESD protection devices during low current long duration stress and its relation to moving current-tubes

Bipolar ESD protection devices subjected to low current long pulse stress can sustain a relatively long time during thermal second breakdown without any damage. The effect is related to a particular current filamentary behavior, which is observed optically by TIM and explained by device simulation. It is also shown that the second breakdown is initiated at the edges of the device when a moving current-tube arrives at the device edge. Thus circular devices, having no edges, exhibit lower risk of second breakdown.

A TLP-based Human Metal Model ESD-generator for device qualification according to IEC 61000-4-2

In the last years system-level electrostatic discharges tests according to IEC 61000-4-2 have become widely used for component ESD qualification although it suffers from poor reproducibility. To minimize the disadvantages a so called Human Metal Model (HMM) measurement technique is momentarily in discussion and the standardization committee (SP5.6, ESDA) is working on its definition. The current stress waveform of HMM is identical to the IEC 61000-4-2 one. In this paper a new HMM pulse generator set-up based on a TLP pulse generator will be discussed. To get a deeper insight in the HMM method, discrete components, on-chip ESD test structures as well as a LIN transceiver were evaluated with this technique. The gained measurement results are compared with those resulting out of the IEC tests.

Avalanche Breakdown Delay in High-Voltage p-n Junctions Caused by Pre-Pulse Voltage From IEC 61000-4-2 ESD Generators

Electrostatic-discharge (ESD) tests with IEC 61000-4-2 generators are often performed at component level but are known to suffer from poor reproducibility. In this paper, it is shown that IEC 61000-4-2 generators can charge the tested device to several tens of volts before the actual ESD pulse is applied. This pre-pulse voltage (PPV) can lead to delayed avalanche breakdown (BD) initiation in silicon junctions. The origin of the BD delay is the emptying of deep trap states within the space-charge region, which lowers the contribution to the generation current due to carrier emission from the deep states. The BD delay is critical for ESD protection devices and can also lead to a dramatic reduction of the snapback trigger current in DMOS transistors. However, transient gate turn-on of the DMOS transistor eliminates the BD delay and can thus increase the ESD robustness. It is shown that the PPV varies strongly between commercial IEC generators, and it is proposed that this could be one of the main reasons for the poor reproducibility of IEC tests. A newly proposed method to deliver an IEC 61000-4-2-shaped pulse through a 50-¿ transmission line is investigated with respect to the correlation with real IEC generators. It is shown that PPV-related issues are not addressed by this method, unless an additional bias voltage is applied during the test. It is also demonstrated that PPV is existent in real-world IEC discharges and must not be neglected for component qualification.

Interaction of traveling current filaments and its relation to a nontrivial thermal breakdown scenario in avalanching bipolar transistor

Traveling multiple current filaments (CFs) are investigated by transient interferometric mapping method in avalanching bipolar n-p-n transistors. The number of CFs can vary for identical current pulses and their averaged number increases with the total current. The CF movement is driven by a temperature gradient in it, caused by the self-heating effect. For pulses of 500 ns duration, the existence of two CFs appears dangerous as it causes a nontrivial premature thermal breakdown (TB), which does not occur when only one CF exists at the same current level. TB occurs due to redistribution of current between the two CFs. The current components flowing through each CF depend on CF temperature and are globally coupled by a fixed device current. When a first CF reaches the device end, it heats up and disappears due to vanishing impact ionization rate in it. When a second traveling CF, taking consequently the whole current, reaches the already preheated device end, a TB event occurs. The transition from two to o...

Effect of Elevated Ambient Temperature on Thermal Breakdown Behavior in BCD ESD Protection Devices Subjected to Long Electrical Overstress Pulses

We investigate the effect of elevated ambient temperature on thermal breakdown (TB) modes in linear-geometry electrostatic discharge (ESD) protection n-p-n transistors of smart power technology subjected to 0.5-1- μs-long ESD pulses. The current transport in these devices has a form of traveling current filaments (CFs) where TB at room temperature occurs at one of the device ends. An increase in ambient temperature gives rise additionally to another failure mode, inside the device. For the failure mode at the device end, the increase of ambient temperature in the range up to 100°C causes shortening of the averaged time to TB 〈tTB〉 by a duration that the CF needs for one round trip over the device width. At ambient temperatures up to 180°C, the TB may occur even at initial triggering CF position inside the device, before the CF starts to move. The ambient temperature at which the transition between CF modes with different 〈tTB〉 occurs is investigated as a function of stress current. Furthermore, inspecting the failure current of devices with different widths shows that there is an equivalence between the effect of increased ambient temperature and the effect of the preheating at the device end by a previous CF passage. The experiments are supported by 3-D thermal simulation of temperature in moving and standing CFs.

A passive coupling circuit for injecting TLP-like stress pulses into only one end of a driver/receiver system

In this paper, a simple passive circuit is presented which allows TLP stress and characterization pulses to be injected into only one side of a driver/receiver system. The circuit is simulated and tested, demonstrating the possibility for directional current injection on the order of 60:1. The circuit also provides a method for measuring both injected currents when paired with a typical TLP system.