Jordi Carrabina

Ion-sensitive field-effect transistors fabricated in a commercial CMOS technology

Abstract The fabrication of pH-sensitive ISFET devices in an unmodified two-metal commercial CMOS technology (1.0 m from Atmel-ES2) is reported. The ISFET devices have a gate structure compatible with the CMOS process, with an electrically floating electrode consisting on polysilicon plus the two metals. The passivation oxynitride layer acts as the pH-sensitive material in contact with the liquid solution. The devices have shown good operating characteristics, with a 47 mV/pH response. The use of a commercial CMOS process allows the straightforward integration of signal-processing circuitry. An ISFET amplifier circuit has been integrated with the ISFET sensors.

Mixed SW/SystemC SoC Emulation Framework

Developing HW modules for standard platforms like PCs or embedded devices requires a complete system emulator availability to detect and fix bugs on developed HW, Operating Systems (OS) drivers and applications. This paper presents a set of plug-ins to an open-source CPU emulator that enables mixed simulations between platforms emulators and hardware (HW) modules described in SystemC. In this paper three plugins for QEMU are described: one for connecting TLM SystemC modules to any bus QEMU emulates, one for connecting SystemC to PCI bus for PC based platform and one plug-in for connecting SystemC to AMBA bus for ARM platforms. With this framework, it is possible to develop OS drivers at the same time HW is developed and final application tested running in this virtual platform.

xENoC - An eXperimental Network-On-Chip Environment for Parallel Distributed Computing on NoC-based MPSoC Architectures

This paper describes xENoC, an automatic and component re-use HW-SW environment to build simulatable and synthesizable Network-on-Chip-based MPSoC architectures. xENoC is based on a tool, named NoCWizard, which uses an eXtensible Markup Language (XML) specification, and a set of modularized components and templates to generate many types of NoC instances by using Verilog HDL. This NoC models can be customized in terms of topology, tile location/mapping, RNIs generation, different types of routers, FIFO and packet/flit sizes, by simply modifying the XML specifications. Furthermore, xENoC is also composed of software components, i.e. RNI drivers and a parallel programming model, embedded Message Passing Interface (eMPI), which let us to carry out a complete HW-SW co-design methodology to design distributed-memory NoC-based MPSoCs parallel applications. Through xENoC different distributed-memory NoC-based MPSoCs designs have been created simulated and prototyped in physical platforms (e.g. FPGA boards), and some parallel multiprocessor test traffic applications are running there as system level demonstrators.

Address Generation Optimization for Embedded High-Performance Processors: A Survey

Nowadays embedded systems are growing at an impressive rate and provide more and more sophisticated applications characterized by having a complex array index manipulation and a large number of data accesses. Those applications require high performance specific computation that general purpose processors can not deliver at a reasonable energy consumption. Very long instruction word architectures seem a good solution providing enough computational performance at low power with the required programmability to speed up the time to market. Those architectures rely on compiler effort to exploit the available instruction and data parallelism to keep the data path busy all the time. With the density of transistors doubling each 18 months, more and more sophisticated architectures with a high number of computational resources running in parallel are emerging. With this increasing parallel computation, the access to data is becoming the main bottleneck that limits the available parallelism. To alleviate this problem, in current embedded architectures, a special unit works in parallel with the main computing elements to ensure efficient feed and storage of the data: the address generator unit, which comes in many flavors. Future architectures will have to deal with enormous memory bandwidth in distributed memories and the development of address generators units will be crucial for effective next generation of embedded processors where global trade-offs between reaction-time, bandwidth, energy and area must be achieved. This paper provides a survey of methods and techniques that optimize the address generation process for embedded systems, explaining current research trends and needs for future.

Power breakdown analysis for a heterogeneous NoC platform running a video application

Users expect future handheld devices to provide extended multimedia functionality and have long battery life. This type of application imposes heavy constraints on performance and power consumption and forces designers to optimize all parts of their platform. Evaluating the overall platform power breakdown is therefore critical to determine where to spend the efforts on power optimization. Surprisingly, few studies exist on that topic and decisions generally rely on common belief. We have realized a complete power breakdown for a realistic platform to identify the major power bottlenecks. This paper presents this power assessment of a realistic heterogeneous network on chip platform including processors, network and data/instruction memory hierarchy, running a video processing chain from camera to display. Our power breakdown identifies the main bottlenecks in the memory hierarchy and the foreground memory, and shows that global interconnect is not that critical for a well-optimized application mapping.

Current Status and Opportunities of Organic Thin-Film Transistor Technologies

Attributed to its advantages of super mechanical flexibility, very low-temperature processing, and compatibility with low cost and high throughput manufacturing, organic thin-film transistor (OTFT) technology is able to bring electrical, mechanical, and industrial benefits to a wide range of new applications by activating nonflat surfaces with flexible displays, sensors, and other electronic functions. Despite both strong application demand and these significant technological advances, there is still a gap to be filled for OTFT technology to be widely commercially adopted. This paper provides a comprehensive review of the current status of OTFT technologies ranging from material, device, process, and integration, to design and system applications, and clarifies the real challenges behind to be addressed.

Simple real-time QRS detector with the MaMeMi filter

Abstract Detection of QRS complexes in ECG signals is required to determine heart rate, and it is an important step in the study of cardiac disorders. ECG signals are usually affected by noise of low and high frequency. To improve the accuracy of QRS detectors several methods have been proposed to filter out the noise and detect the characteristic pattern of QRS complex. Most of the existing methods are at a disadvantage from relatively high computational complexity or high resource needs making them less optimized for its implementation on portable embedded systems, wearable devices or ultra-low power chips. We present a new method to detect the QRS signal in a simple way with minimal computational cost and resource needs using a novel non-linear filter.

Inkjet patterning of multiline intersections for wirings in printed electronics.

Inkjet printed electronics using thermo-curable liquid inks exhibit particular geometrical characteristics in terms of regularity. This article presents a morphological analysis for inkjet printed multi line intersections that are critical structures for building circuits. We studied thin-film structures of silver conductive ink and printed by inkjet technology. Instability of the ink during printing causes the thickness irregularity of vertex, normally with peaks at these areas. We propose the usage of specific patterns for intersections as thickness regularity compensations. The results show that some patterns help to reduce this instability and improve the thickness regularity of intersections morphology.

Front-End ADC Requirements for Uniform Bandpass Sampling in SDR

Changing user scenarios demand wireless connectivity among different standards. As a result, reconfigurability is becoming a key issue in the design of future wireless terminals. In analog front-ends, reconfigurable components are very expensive in terms of design cost and area. Bandpass sampling and digital front-end solutions in general, move the ADC closer to the antenna, avoiding most of the reconfigurable analog hardware. We consider the extreme case of bandpass sampling at RF and analyze the ADC requirements for a multi-standard radio. Two different models, one based on cascade analysis and the other on time-domain simulations, are used with a representative set of emerging wireless standards to derive the ADC requirements: sampling frequency, resolution and clock jitter. This study shows that, with modest RF filtering, RF bandpass sampling will soon become a reality for low power terminals.

All-inkjet printed organic transistors: Dielectric surface passivation techniques for improved operational stability and lifetime

Abstract We report about the use of a printed pentafluorothiophenol layer on top of the dielectric surface as a passivation coating to improve the operational stability of all-ink-jet printed transistors. Transistors with bottom-gate structure were fabricated using cross-linked poly-4-vinylphenol (c-PVP) as dielectric layer and an ink formulation of an amorphous triarylamine polymer as semiconductor. The resulting TFTs had low turn-on voltage (Vth